| Message ID | 20201217180638.22748-8-digetx@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs | expand |
On Thu, Dec 17, 2020 at 09:05:57PM +0300, Dmitry Osipenko wrote: > All NVIDIA Tegra SoCs have a core power domain where majority of hardware > blocks reside. Add binding for the core power domain. > > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > .../arm/tegra/nvidia,tegra20-core-domain.yaml | 48 +++++++++++++++++++ > 1 file changed, 48 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml > > diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml > new file mode 100644 > index 000000000000..f3d8fd2d8371 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml > @@ -0,0 +1,48 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-core-domain.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NVIDIA Tegra Core Power Domain > + > +maintainers: > + - Dmitry Osipenko <digetx@gmail.com> > + - Jon Hunter <jonathanh@nvidia.com> > + - Thierry Reding <thierry.reding@gmail.com> > + > +properties: > + compatible: > + enum: > + - nvidia,tegra20-core-domain > + - nvidia,tegra30-core-domain The file should be in bindings/power. Include also the power-domain.yaml schema. > + > + operating-points-v2: > + description: > + Should contain level, voltages and opp-supported-hw property. > + The supported-hw is a bitfield indicating SoC speedo or process > + ID mask. > + > + "#power-domain-cells": > + const: 0 > + > + power-supply: > + description: > + Phandle to voltage regulator connected to the SoC Core power rail. > + > +required: > + - compatible > + - operating-points-v2 > + - "#power-domain-cells" > + - power-supply > + > +additionalProperties: false > + > +examples: > + - | > + core-domain { power-domain (to follow schema and devicetree spec) Best regards, Krzysztof > + compatible = "nvidia,tegra20-core-domain"; > + operating-points-v2 = <&opp_table>; > + power-supply = <®ulator>; > + #power-domain-cells = <0>; > + }; > -- > 2.29.2 >
19.12.2020 13:57, Krzysztof Kozlowski пишет: > On Thu, Dec 17, 2020 at 09:05:57PM +0300, Dmitry Osipenko wrote: >> All NVIDIA Tegra SoCs have a core power domain where majority of hardware >> blocks reside. Add binding for the core power domain. >> >> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> >> --- >> .../arm/tegra/nvidia,tegra20-core-domain.yaml | 48 +++++++++++++++++++ >> 1 file changed, 48 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml >> >> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml >> new file mode 100644 >> index 000000000000..f3d8fd2d8371 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml >> @@ -0,0 +1,48 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-core-domain.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: NVIDIA Tegra Core Power Domain >> + >> +maintainers: >> + - Dmitry Osipenko <digetx@gmail.com> >> + - Jon Hunter <jonathanh@nvidia.com> >> + - Thierry Reding <thierry.reding@gmail.com> >> + >> +properties: >> + compatible: >> + enum: >> + - nvidia,tegra20-core-domain >> + - nvidia,tegra30-core-domain > > The file should be in bindings/power. > Include also the power-domain.yaml schema. > >> + >> + operating-points-v2: >> + description: >> + Should contain level, voltages and opp-supported-hw property. >> + The supported-hw is a bitfield indicating SoC speedo or process >> + ID mask. >> + >> + "#power-domain-cells": >> + const: 0 >> + >> + power-supply: >> + description: >> + Phandle to voltage regulator connected to the SoC Core power rail. >> + >> +required: >> + - compatible >> + - operating-points-v2 >> + - "#power-domain-cells" >> + - power-supply >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + core-domain { > > power-domain (to follow schema and devicetree spec) Thanks for the suggestion, I'll update it in v3.
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml new file mode 100644 index 000000000000..f3d8fd2d8371 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-core-domain.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Core Power Domain + +maintainers: + - Dmitry Osipenko <digetx@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + - Thierry Reding <thierry.reding@gmail.com> + +properties: + compatible: + enum: + - nvidia,tegra20-core-domain + - nvidia,tegra30-core-domain + + operating-points-v2: + description: + Should contain level, voltages and opp-supported-hw property. + The supported-hw is a bitfield indicating SoC speedo or process + ID mask. + + "#power-domain-cells": + const: 0 + + power-supply: + description: + Phandle to voltage regulator connected to the SoC Core power rail. + +required: + - compatible + - operating-points-v2 + - "#power-domain-cells" + - power-supply + +additionalProperties: false + +examples: + - | + core-domain { + compatible = "nvidia,tegra20-core-domain"; + operating-points-v2 = <&opp_table>; + power-supply = <®ulator>; + #power-domain-cells = <0>; + };
All NVIDIA Tegra SoCs have a core power domain where majority of hardware blocks reside. Add binding for the core power domain. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- .../arm/tegra/nvidia,tegra20-core-domain.yaml | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml