| Message ID | 20201228112715.14947-2-wsa+renesas@sang-engineering.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | v3u: add & update (H)SCIF nodes | expand |
Hi Wolfram, On Mon, Dec 28, 2020 at 12:27 PM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: Missing "From: Linh Phung <linh.phung.jy@renesas.com>"? > This is the result of multiple patches taken from the BSP, combined, > rebased, and properly sorted. SCIF0 gets DMA properties, other SCIFs are > entirely new. > > Signed-off-by: Linh Phung <linh.phung.jy@renesas.com> > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Thanks for your patch! > --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi > @@ -656,11 +656,61 @@ scif0: serial@e6e60000 { > <&cpg CPG_CORE R8A779A0_CLK_S1D2>, > <&scif_clk>; > clock-names = "fck", "brg_int", "scif_clk"; > + dmas = <&dmac1 0x51>, <&dmac1 0x50>; > + dma-names = "tx", "rx"; It may be prudent to leave out the DMA properties until we can validate DMA operation. > power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; > resets = <&cpg 702>; > status = "disabled"; > }; > > + scif1: serial@e6e68000 { > + compatible = "renesas,scif-r8a779a0", > + "renesas,rcar-gen3-scif", "renesas,scif"; > + reg = <0 0xe6e68000 0 64>; > + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 703>, > + <&cpg CPG_CORE R8A779A0_CLK_S1D2>, > + <&scif_clk>; > + clock-names = "fck", "brg_int", "scif_clk"; > + dmas = <&dmac1 0x53>, <&dmac1 0x52>; > + dma-names = "tx", "rx"; > + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; > + resets = <&cpg 703>; > + status = "disabled"; > + }; > + > + scif4: serial@e6c40000 { > + compatible = "renesas,scif-r8a779a0", > + "renesas,rcar-gen3-scif", "renesas,scif"; > + reg = <0 0xe6c40000 0 64>; > + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 705>, > + <&cpg CPG_CORE R8A779A0_CLK_S1D2>, > + <&scif_clk>; > + clock-names = "fck", "brg_int", "scif_clk"; > + dmas = <&dmac1 0x59>, <&dmac1 0x58>; > + dma-names = "tx", "rx"; > + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; > + resets = <&cpg 705>; > + status = "disabled"; > + }; > + > + scif3: serial@e6c50000 { Please move scif3 before scif4. > + compatible = "renesas,scif-r8a779a0", > + "renesas,rcar-gen3-scif", "renesas,scif"; > + reg = <0 0xe6c50000 0 64>; > + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 704>, > + <&cpg CPG_CORE R8A779A0_CLK_S1D2>, > + <&scif_clk>; > + clock-names = "fck", "brg_int", "scif_clk"; > + dmas = <&dmac1 0x57>, <&dmac1 0x56>; > + dma-names = "tx", "rx"; > + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; > + resets = <&cpg 704>; > + status = "disabled"; > + }; > + With the above fixed: Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
> > + scif3: serial@e6c50000 { > > Please move scif3 before scif4. I thought we are sorting by reg value?
Hi Wolfram, On Thu, Jan 14, 2021 at 9:57 PM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > > > + scif3: serial@e6c50000 { > > > > Please move scif3 before scif4. > > I thought we are sorting by reg value? Yeah, but we group nodes of the same type, and sort them by label within the group. We really need a script to take care of the sorting... Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 68aaa49c3540..583cf2e232a0 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -656,11 +656,61 @@ scif0: serial@e6e60000 { <&cpg CPG_CORE R8A779A0_CLK_S1D2>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>; + dma-names = "tx", "rx"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 702>; status = "disabled"; }; + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a779a0", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>, + <&cpg CPG_CORE R8A779A0_CLK_S1D2>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a779a0", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 705>, + <&cpg CPG_CORE R8A779A0_CLK_S1D2>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x59>, <&dmac1 0x58>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 705>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a779a0", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 704>, + <&cpg CPG_CORE R8A779A0_CLK_S1D2>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x57>, <&dmac1 0x56>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + }; + dmac1: dma-controller@e7350000 { reg = <0 0xe7350000 0 0x1000>; #dma-cells = <1>;