| Message ID | 1608715847-28956-2-git-send-email-EastL.Lee@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v8,1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings | expand |
On Wed, Dec 23, 2020 at 05:30:44PM +0800, EastL Lee wrote: > Document the devicetree bindings for MediaTek Command-Queue DMA controller > which could be found on MT6779 SoC or other similar Mediatek SoCs. > > Signed-off-by: EastL Lee <EastL.Lee@mediatek.com> > --- > .../devicetree/bindings/dma/mtk-cqdma.yaml | 104 +++++++++++++++++++++ Use compatible string for filename: mediatek,cqdma.yaml > 1 file changed, 104 insertions(+) > create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.yaml > > diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml > new file mode 100644 > index 0000000..a76a263 > --- /dev/null > +++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml > @@ -0,0 +1,104 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/dma/mtk-cqdma.yaml# Don't forget to update this. > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek Command-Queue DMA controller Device Tree Binding > + > +maintainers: > + - EastL Lee <EastL.Lee@mediatek.com> > + > +description: > + MediaTek Command-Queue DMA controller (CQDMA) on Mediatek SoC > + is dedicated to memory-to-memory transfer through queue based > + descriptor management. > + > +allOf: > + - $ref: "dma-controller.yaml#" > + > +properties: > + compatible: > + items: > + - enum: > + - mediatek,mt6765-cqdma > + - mediatek,mt6779-cqdma > + - const: mediatek,cqdma > + > + reg: > + minItems: 1 > + maxItems: 5 > + description: > + A base address of MediaTek Command-Queue DMA controller, > + a channel will have a set of base address. > + > + interrupts: > + minItems: 1 > + maxItems: 5 > + description: > + A interrupt number of MediaTek Command-Queue DMA controller, > + one interrupt number per dma-channels. > + > + clocks: > + maxItems: 1 > + > + clock-names: > + const: cqdma > + > + dma-channel-mask: > + description: > + For DMA capability, We will know the addressing capability of > + MediaTek Command-Queue DMA controller through dma-channel-mask. > + minimum: 1 > + maximum: 63 Indentation is wrong here so this has no effect. A mask of 63 is 6 channels... > + > + dma-channels: > + description: > + Number of DMA channels supported by MediaTek Command-Queue DMA > + controller, support up to five. > + minimum: 1 > + maximum: 5 Same here. Do you really need both dma-channels and dma-channel-mask? You should be able to get one from the other. > + > + dma-requests: > + description: > + Number of DMA request (virtual channel) supported by MediaTek > + Command-Queue DMA controller, support up to 32. > + minimum: 1 > + maximum: 32 And here. You are missing '#dma-cells' also. > + > +required: > + - "#dma-cells" > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - dma-channel-mask > + - dma-channels > + - dma-requests > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/clock/mt6779-clk.h> > + cqdma: dma-controller@10212000 { > + compatible = "mediatek,mt6779-cqdma"; This should fail validation because it doesn't match the schema. You ran 'make dt_binding_check', right? > + reg = <0x10212000 0x80>, > + <0x10212080 0x80>, > + <0x10212100 0x80>; > + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>, > + <GIC_SPI 140 IRQ_TYPE_LEVEL_LOW>, > + <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg_ao CLK_INFRA_CQ_DMA>; > + clock-names = "cqdma"; > + dma-channel-mask = <63>; 6 channels or... > + dma-channels = <3>; 3? > + dma-requests = <32>; > + #dma-cells = <1>; > + }; > + > +... > -- > 1.9.1 >
On Sun, 2021-01-03 at 09:58 -0700, Rob Herring wrote: > On Wed, Dec 23, 2020 at 05:30:44PM +0800, EastL Lee wrote: > > Document the devicetree bindings for MediaTek Command-Queue DMA controller > > which could be found on MT6779 SoC or other similar Mediatek SoCs. > > > > Signed-off-by: EastL Lee <EastL.Lee@mediatek.com> > > --- > > .../devicetree/bindings/dma/mtk-cqdma.yaml | 104 +++++++++++++++++++++ > > Use compatible string for filename: OK > > mediatek,cqdma.yaml > > > 1 file changed, 104 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.yaml > > > > diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml > > new file mode 100644 > > index 0000000..a76a263 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml > > @@ -0,0 +1,104 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/dma/mtk-cqdma.yaml# > > Don't forget to update this. OK > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: MediaTek Command-Queue DMA controller Device Tree Binding > > + > > +maintainers: > > + - EastL Lee <EastL.Lee@mediatek.com> > > + > > +description: > > + MediaTek Command-Queue DMA controller (CQDMA) on Mediatek SoC > > + is dedicated to memory-to-memory transfer through queue based > > + descriptor management. > > + > > +allOf: > > + - $ref: "dma-controller.yaml#" > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - mediatek,mt6765-cqdma > > + - mediatek,mt6779-cqdma > > + - const: mediatek,cqdma > > + > > + reg: > > + minItems: 1 > > + maxItems: 5 > > + description: > > + A base address of MediaTek Command-Queue DMA controller, > > + a channel will have a set of base address. > > + > > + interrupts: > > + minItems: 1 > > + maxItems: 5 > > + description: > > + A interrupt number of MediaTek Command-Queue DMA controller, > > + one interrupt number per dma-channels. > > + > > + clocks: > > + maxItems: 1 > > + > > + clock-names: > > + const: cqdma > > + > > + dma-channel-mask: > > + description: > > + For DMA capability, We will know the addressing capability of > > + MediaTek Command-Queue DMA controller through dma-channel-mask. > > + minimum: 1 > > + maximum: 63 > > Indentation is wrong here so this has no effect. I'll fix it > > A mask of 63 is 6 channels... In my opinion, kernel dma mask if for 32/64 bit capability... If I don't set dma mask I will get fail on DMATEST. > > > + > > + dma-channels: > > + description: > > + Number of DMA channels supported by MediaTek Command-Queue DMA > > + controller, support up to five. > > + minimum: 1 > > + maximum: 5 > > Same here. OK > > Do you really need both dma-channels and dma-channel-mask? You should be > able to get one from the other. > > > + > > + dma-requests: > > + description: > > + Number of DMA request (virtual channel) supported by MediaTek > > + Command-Queue DMA controller, support up to 32. > > + minimum: 1 > > + maximum: 32 > > And here. > > You are missing '#dma-cells' also. OK I'll fix it. > > > + > > +required: > > + - "#dma-cells" > > + - compatible > > + - reg > > + - interrupts > > + - clocks > > + - clock-names > > + - dma-channel-mask > > + - dma-channels > > + - dma-requests > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/irq.h> > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + #include <dt-bindings/clock/mt6779-clk.h> > > + cqdma: dma-controller@10212000 { > > + compatible = "mediatek,mt6779-cqdma"; > > This should fail validation because it doesn't match the schema. You ran > 'make dt_binding_check', right? Yes, but I got other fail on kernel-5.10... > > > + reg = <0x10212000 0x80>, > > + <0x10212080 0x80>, > > + <0x10212100 0x80>; > > + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>, > > + <GIC_SPI 140 IRQ_TYPE_LEVEL_LOW>, > > + <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>; > > + clocks = <&infracfg_ao CLK_INFRA_CQ_DMA>; > > + clock-names = "cqdma"; > > + dma-channel-mask = <63>; > > 6 channels or... > > > + dma-channels = <3>; > > 3? 3 channel, the mask is for DMATEST PASS. > > > + dma-requests = <32>; > > + #dma-cells = <1>; > > + }; > > + > > +... > > -- > > 1.9.1 > >
On Wed, Jan 6, 2021 at 2:25 AM EastL <EastL.Lee@mediatek.com> wrote: > > On Sun, 2021-01-03 at 09:58 -0700, Rob Herring wrote: > > On Wed, Dec 23, 2020 at 05:30:44PM +0800, EastL Lee wrote: > > > Document the devicetree bindings for MediaTek Command-Queue DMA controller > > > which could be found on MT6779 SoC or other similar Mediatek SoCs. > > > > > > Signed-off-by: EastL Lee <EastL.Lee@mediatek.com> > > > --- > > > .../devicetree/bindings/dma/mtk-cqdma.yaml | 104 +++++++++++++++++++++ > > > > Use compatible string for filename: > OK > > > > mediatek,cqdma.yaml > > > > > 1 file changed, 104 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml > > > new file mode 100644 > > > index 0000000..a76a263 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml > > > @@ -0,0 +1,104 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/dma/mtk-cqdma.yaml# > > > > Don't forget to update this. > OK > > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: MediaTek Command-Queue DMA controller Device Tree Binding > > > + > > > +maintainers: > > > + - EastL Lee <EastL.Lee@mediatek.com> > > > + > > > +description: > > > + MediaTek Command-Queue DMA controller (CQDMA) on Mediatek SoC > > > + is dedicated to memory-to-memory transfer through queue based > > > + descriptor management. > > > + > > > +allOf: > > > + - $ref: "dma-controller.yaml#" > > > + > > > +properties: > > > + compatible: > > > + items: > > > + - enum: > > > + - mediatek,mt6765-cqdma > > > + - mediatek,mt6779-cqdma > > > + - const: mediatek,cqdma > > > + > > > + reg: > > > + minItems: 1 > > > + maxItems: 5 > > > + description: > > > + A base address of MediaTek Command-Queue DMA controller, > > > + a channel will have a set of base address. > > > + > > > + interrupts: > > > + minItems: 1 > > > + maxItems: 5 > > > + description: > > > + A interrupt number of MediaTek Command-Queue DMA controller, > > > + one interrupt number per dma-channels. > > > + > > > + clocks: > > > + maxItems: 1 > > > + > > > + clock-names: > > > + const: cqdma > > > + > > > + dma-channel-mask: > > > + description: > > > + For DMA capability, We will know the addressing capability of > > > + MediaTek Command-Queue DMA controller through dma-channel-mask. > > > + minimum: 1 > > > + maximum: 63 > > > > Indentation is wrong here so this has no effect. > I'll fix it > > > > A mask of 63 is 6 channels... > In my opinion, kernel dma mask if for 32/64 bit capability... > If I don't set dma mask I will get fail on DMATEST. As in the kernel's 'dma_mask'? That's something entirely different. The driver should set the mask to the max the device supports. Typically this is a 32-bit or 64-bit mask. The default is 32-bit. If the SoC has limitations in its buses, then you need to use 'dma-ranges' in DT which will in turn set the bus_dma_limit. For the above, the purpose is if you have sparsely allocated DMA channels. Rob
On 06-01-21, 16:53, Rob Herring wrote: > > > > + dma-channel-mask: > > > > + description: > > > > + For DMA capability, We will know the addressing capability of > > > > + MediaTek Command-Queue DMA controller through dma-channel-mask. > > > > + minimum: 1 > > > > + maximum: 63 > > > > > > Indentation is wrong here so this has no effect. > > I'll fix it > > > > > > A mask of 63 is 6 channels... > > In my opinion, kernel dma mask if for 32/64 bit capability... > > If I don't set dma mask I will get fail on DMATEST. > > As in the kernel's 'dma_mask'? That's something entirely different. > The driver should set the mask to the max the device supports. > Typically this is a 32-bit or 64-bit mask. The default is 32-bit. If > the SoC has limitations in its buses, then you need to use > 'dma-ranges' in DT which will in turn set the bus_dma_limit. Correct, dma_mask tells dmatest the capability of the device and should be set accordingly dma-channel-mask defines the 'Bitmask of available DMA channels' and is deined in dma-common.yaml
diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml new file mode 100644 index 0000000..a76a263 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/mtk-cqdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Command-Queue DMA controller Device Tree Binding + +maintainers: + - EastL Lee <EastL.Lee@mediatek.com> + +description: + MediaTek Command-Queue DMA controller (CQDMA) on Mediatek SoC + is dedicated to memory-to-memory transfer through queue based + descriptor management. + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + items: + - enum: + - mediatek,mt6765-cqdma + - mediatek,mt6779-cqdma + - const: mediatek,cqdma + + reg: + minItems: 1 + maxItems: 5 + description: + A base address of MediaTek Command-Queue DMA controller, + a channel will have a set of base address. + + interrupts: + minItems: 1 + maxItems: 5 + description: + A interrupt number of MediaTek Command-Queue DMA controller, + one interrupt number per dma-channels. + + clocks: + maxItems: 1 + + clock-names: + const: cqdma + + dma-channel-mask: + description: + For DMA capability, We will know the addressing capability of + MediaTek Command-Queue DMA controller through dma-channel-mask. + minimum: 1 + maximum: 63 + + dma-channels: + description: + Number of DMA channels supported by MediaTek Command-Queue DMA + controller, support up to five. + minimum: 1 + maximum: 5 + + dma-requests: + description: + Number of DMA request (virtual channel) supported by MediaTek + Command-Queue DMA controller, support up to 32. + minimum: 1 + maximum: 32 + +required: + - "#dma-cells" + - compatible + - reg + - interrupts + - clocks + - clock-names + - dma-channel-mask + - dma-channels + - dma-requests + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/mt6779-clk.h> + cqdma: dma-controller@10212000 { + compatible = "mediatek,mt6779-cqdma"; + reg = <0x10212000 0x80>, + <0x10212080 0x80>, + <0x10212100 0x80>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg_ao CLK_INFRA_CQ_DMA>; + clock-names = "cqdma"; + dma-channel-mask = <63>; + dma-channels = <3>; + dma-requests = <32>; + #dma-cells = <1>; + }; + +... -- 1.9.1
Document the devicetree bindings for MediaTek Command-Queue DMA controller which could be found on MT6779 SoC or other similar Mediatek SoCs. Signed-off-by: EastL Lee <EastL.Lee@mediatek.com> --- .../devicetree/bindings/dma/mtk-cqdma.yaml | 104 +++++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.yaml