| Message ID | 1608717823-18387-12-git-send-email-anshuman.khandual@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: coresight: Enable ETE and TRBE | expand |
On Wed, Dec 23, 2020 at 03:33:43PM +0530, Anshuman Khandual wrote: > This patch documents the device tree binding in use for Arm TRBE. > > Cc: devicetree@vger.kernel.org > Cc: Mathieu Poirier <mathieu.poirier@linaro.org> > Cc: Mike Leach <mike.leach@linaro.org> > Cc: Suzuki K Poulose <suzuki.poulose@arm.com> > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> > --- > Changes in V1: > > - TRBE DT entry has been renamed as 'arm, trace-buffer-extension' > > Documentation/devicetree/bindings/arm/trbe.txt | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/trbe.txt > > diff --git a/Documentation/devicetree/bindings/arm/trbe.txt b/Documentation/devicetree/bindings/arm/trbe.txt > new file mode 100644 > index 0000000..001945d > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/trbe.txt > @@ -0,0 +1,20 @@ > +* Trace Buffer Extension (TRBE) > + > +Trace Buffer Extension (TRBE) is used for collecting trace data generated > +from a corresponding trace unit (ETE) using an in memory trace buffer. > + > +** TRBE Required properties: > + > +- compatible : should be one of: > + "arm,trace-buffer-extension" > + > +- interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where > + TRBE is only supported on a subset of the CPUs, please consult > + the arm,gic-v3 binding for details on describing a PPI partition. > + > +** Example: > + > +trbe { > + compatible = "arm,trace-buffer-extension"; > + interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; If only an interrupt, then could just be part of ETE? If not, how is this hardware block accessed? An interrupt alone is not enough unless there's some architected way to access. Rob
On 1/3/21 10:35 PM, Rob Herring wrote: > On Wed, Dec 23, 2020 at 03:33:43PM +0530, Anshuman Khandual wrote: >> This patch documents the device tree binding in use for Arm TRBE. >> >> Cc: devicetree@vger.kernel.org >> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> >> Cc: Mike Leach <mike.leach@linaro.org> >> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> >> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> >> --- >> Changes in V1: >> >> - TRBE DT entry has been renamed as 'arm, trace-buffer-extension' >> >> Documentation/devicetree/bindings/arm/trbe.txt | 20 ++++++++++++++++++++ >> 1 file changed, 20 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/arm/trbe.txt >> >> diff --git a/Documentation/devicetree/bindings/arm/trbe.txt b/Documentation/devicetree/bindings/arm/trbe.txt >> new file mode 100644 >> index 0000000..001945d >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/arm/trbe.txt >> @@ -0,0 +1,20 @@ >> +* Trace Buffer Extension (TRBE) >> + >> +Trace Buffer Extension (TRBE) is used for collecting trace data generated >> +from a corresponding trace unit (ETE) using an in memory trace buffer. >> + >> +** TRBE Required properties: >> + >> +- compatible : should be one of: >> + "arm,trace-buffer-extension" >> + >> +- interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where >> + TRBE is only supported on a subset of the CPUs, please consult >> + the arm,gic-v3 binding for details on describing a PPI partition. >> + >> +** Example: >> + >> +trbe { >> + compatible = "arm,trace-buffer-extension"; >> + interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; > > If only an interrupt, then could just be part of ETE? If not, how is > this hardware block accessed? An interrupt alone is not enough unless > there's some architected way to access. TRBE hardware block is accessed via respective new system registers but the PPI number where the IRQ will be triggered for various buffer events, would depend on the platform as defined in the SBSA. TRBE would need a ETE to work but the reverse is not true. ETE might just be present without a corresponding TRBE and can work with traditional sinks. Hence just wondering whether it would be prudent to add the TRBE interrupt number as part of the ETE DT specification.
On 1/4/21 3:44 AM, Anshuman Khandual wrote: > > On 1/3/21 10:35 PM, Rob Herring wrote: >> On Wed, Dec 23, 2020 at 03:33:43PM +0530, Anshuman Khandual wrote: >>> This patch documents the device tree binding in use for Arm TRBE. >>> >>> Cc: devicetree@vger.kernel.org >>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> >>> Cc: Mike Leach <mike.leach@linaro.org> >>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> >>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> >>> --- >>> Changes in V1: >>> >>> - TRBE DT entry has been renamed as 'arm, trace-buffer-extension' >>> >>> Documentation/devicetree/bindings/arm/trbe.txt | 20 ++++++++++++++++++++ >>> 1 file changed, 20 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/arm/trbe.txt >>> >>> diff --git a/Documentation/devicetree/bindings/arm/trbe.txt b/Documentation/devicetree/bindings/arm/trbe.txt >>> new file mode 100644 >>> index 0000000..001945d >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/arm/trbe.txt >>> @@ -0,0 +1,20 @@ >>> +* Trace Buffer Extension (TRBE) >>> + >>> +Trace Buffer Extension (TRBE) is used for collecting trace data generated >>> +from a corresponding trace unit (ETE) using an in memory trace buffer. >>> + >>> +** TRBE Required properties: >>> + >>> +- compatible : should be one of: >>> + "arm,trace-buffer-extension" >>> + >>> +- interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where >>> + TRBE is only supported on a subset of the CPUs, please consult >>> + the arm,gic-v3 binding for details on describing a PPI partition. >>> + >>> +** Example: >>> + >>> +trbe { >>> + compatible = "arm,trace-buffer-extension"; >>> + interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; >> >> If only an interrupt, then could just be part of ETE? If not, how is >> this hardware block accessed? An interrupt alone is not enough unless >> there's some architected way to access. > > TRBE hardware block is accessed via respective new system registers but the > PPI number where the IRQ will be triggered for various buffer events, would > depend on the platform as defined in the SBSA. That is correct. TRBE is accessed via CPU system registers. The IRQ is specifically for the TRBE unit to handle buffer overflow situations and other errors in the buffer handling. Please include this information in the description section of the bindings. Also, it may be worth switching this to yaml format. Suzuki
diff --git a/Documentation/devicetree/bindings/arm/trbe.txt b/Documentation/devicetree/bindings/arm/trbe.txt new file mode 100644 index 0000000..001945d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/trbe.txt @@ -0,0 +1,20 @@ +* Trace Buffer Extension (TRBE) + +Trace Buffer Extension (TRBE) is used for collecting trace data generated +from a corresponding trace unit (ETE) using an in memory trace buffer. + +** TRBE Required properties: + +- compatible : should be one of: + "arm,trace-buffer-extension" + +- interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where + TRBE is only supported on a subset of the CPUs, please consult + the arm,gic-v3 binding for details on describing a PPI partition. + +** Example: + +trbe { + compatible = "arm,trace-buffer-extension"; + interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; +};
This patch documents the device tree binding in use for Arm TRBE. Cc: devicetree@vger.kernel.org Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> --- Changes in V1: - TRBE DT entry has been renamed as 'arm, trace-buffer-extension' Documentation/devicetree/bindings/arm/trbe.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/trbe.txt