| Message ID | 1610000348-17316-3-git-send-email-TonyWWang-oc@zhaoxin.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Herbert Xu |
| Headers | show |
| Series | crypto: x86/crc32c-intel - Exclude some Zhaoxin CPUs | expand |
On 1/6/21 10:19 PM, Tony W Wang-oc wrote: > + /* > + * These CPUs declare support SSE4.2 instruction sets but > + * having low performance CRC32C instruction implementation. > + */ > + if (c->x86 == 0x6 || (c->x86 == 0x7 && c->x86_model <= 0x3b)) > + set_cpu_cap(c, X86_FEATURE_CRC32C); > } On the Intel side, we've tried to move away from open-coded model numbers. Say another CPU is released that has a microarchitecture close to 0x3b, but has a model of 0x3c. It's a *LOT* easier to grep for INTEL_FAM6_NEHALEM (or whatever) than 0x3c. See: arch/x86/include/asm/intel-family.h for examples.
On 07/01/2021 23:52, Dave Hansen wrote: > On 1/6/21 10:19 PM, Tony W Wang-oc wrote: >> + /* >> + * These CPUs declare support SSE4.2 instruction sets but >> + * having low performance CRC32C instruction implementation. >> + */ >> + if (c->x86 == 0x6 || (c->x86 == 0x7 && c->x86_model <= 0x3b)) >> + set_cpu_cap(c, X86_FEATURE_CRC32C); >> } > > On the Intel side, we've tried to move away from open-coded model > numbers. Say another CPU is released that has a microarchitecture close > to 0x3b, but has a model of 0x3c. It's a *LOT* easier to grep for > INTEL_FAM6_NEHALEM (or whatever) than 0x3c. See: > > arch/x86/include/asm/intel-family.h > > for examples. > . > Got it, thanks for your suggestion. Sincerely Tonyw
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c index 345f7d9..13e6fbe 100644 --- a/arch/x86/kernel/cpu/centaur.c +++ b/arch/x86/kernel/cpu/centaur.c @@ -109,6 +109,13 @@ static void early_init_centaur(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); } + + /* + * These CPUs declare support SSE4.2 instruction sets but + * having low performance CRC32C instruction implementation. + */ + if (c->x86 == 0x6 || (c->x86 == 0x7 && c->x86_model <= 0x3b)) + set_cpu_cap(c, X86_FEATURE_CRC32C); } static void init_centaur(struct cpuinfo_x86 *c) diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c index 05fa4ef..837ec65 100644 --- a/arch/x86/kernel/cpu/zhaoxin.c +++ b/arch/x86/kernel/cpu/zhaoxin.c @@ -79,6 +79,12 @@ static void early_init_zhaoxin(struct cpuinfo_x86 *c) c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff); } + /* + * These CPUs declare support SSE4.2 instruction sets but + * having low performance CRC32C instruction implementation. + */ + if (c->x86 == 0x6 || (c->x86 == 0x7 && c->x86_model <= 0x3b)) + set_cpu_cap(c, X86_FEATURE_CRC32C); } static void init_zhaoxin(struct cpuinfo_x86 *c)
Some Zhaoxin CPUs declare support SSE4.2 instruction sets but having a CRC32C instruction implementation that not working as intended. Set low performance CRC32C flag on these CPUs for later use. Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com> --- arch/x86/kernel/cpu/centaur.c | 7 +++++++ arch/x86/kernel/cpu/zhaoxin.c | 6 ++++++ 2 files changed, 13 insertions(+)