| Message ID | 20210107123859.674252-26-suzuki.poulose@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | coresight: etm4x: Support for system instructions | expand |
On Thu, Jan 07, 2021 at 12:38:58PM +0000, Suzuki K Poulose wrote: > From: Jonathan Zhou <jonathan.zhouwen@huawei.com> > > Add definitions for the Arm v8.4 SelfHosted trace extensions registers. > > Acked-by: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Signed-off-by: Jonathan Zhou <jonathan.zhouwen@huawei.com> > [ split the register definitions to separate patch > rename some of the symbols ] > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org> > --- > arch/arm64/include/asm/sysreg.h | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 8b5e7e5c3cc8..4acff97519b9 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -191,6 +191,7 @@ > #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) > > #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0) > +#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) > > #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0) > #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1) > @@ -471,6 +472,7 @@ > > #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0) > #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0) > +#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) > #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) > #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) > #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) > @@ -829,6 +831,7 @@ > #define ID_AA64MMFR2_CNP_SHIFT 0 > > /* id_aa64dfr0 */ > +#define ID_AA64DFR0_TRACE_FILT_SHIFT 40 > #define ID_AA64DFR0_DOUBLELOCK_SHIFT 36 > #define ID_AA64DFR0_PMSVER_SHIFT 32 > #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 > @@ -1003,6 +1006,14 @@ > /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ > #define SYS_MPIDR_SAFE_VAL (BIT(31)) > > +#define TRFCR_ELx_TS_SHIFT 5 > +#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT) > +#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT) > +#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT) > +#define TRFCR_EL2_CX BIT(3) > +#define TRFCR_ELx_ExTRE BIT(1) > +#define TRFCR_ELx_E0TRE BIT(0) > + > #ifdef __ASSEMBLY__ > > .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 > -- > 2.24.1 >
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 8b5e7e5c3cc8..4acff97519b9 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -191,6 +191,7 @@ #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0) +#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0) #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1) @@ -471,6 +472,7 @@ #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0) #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0) +#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) @@ -829,6 +831,7 @@ #define ID_AA64MMFR2_CNP_SHIFT 0 /* id_aa64dfr0 */ +#define ID_AA64DFR0_TRACE_FILT_SHIFT 40 #define ID_AA64DFR0_DOUBLELOCK_SHIFT 36 #define ID_AA64DFR0_PMSVER_SHIFT 32 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 @@ -1003,6 +1006,14 @@ /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ #define SYS_MPIDR_SAFE_VAL (BIT(31)) +#define TRFCR_ELx_TS_SHIFT 5 +#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT) +#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT) +#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT) +#define TRFCR_EL2_CX BIT(3) +#define TRFCR_ELx_ExTRE BIT(1) +#define TRFCR_ELx_E0TRE BIT(0) + #ifdef __ASSEMBLY__ .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30