diff mbox series

[1/2] Enumerate AVX Vector Neural Network instructions

Message ID 20210105004909.42000-2-yang.zhong@intel.com (mailing list archive)
State New, archived
Headers show
Series Enumerate and expose AVX_VNNI feature | expand

Commit Message

Yang Zhong Jan. 5, 2021, 12:49 a.m. UTC
From: Kyung Min Park <kyung.min.park@intel.com>

Add AVX version of the Vector Neural Network (VNNI) Instructions.

A processor supports AVX VNNI instructions if CPUID.0x07.0x1:EAX[4] is
present. The following instructions are available when this feature is
present.
  1. VPDPBUS: Multiply and Add Unsigned and Signed Bytes
  2. VPDPBUSDS: Multiply and Add Unsigned and Signed Bytes with Saturation
  3. VPDPWSSD: Multiply and Add Signed Word Integers
  4. VPDPWSSDS: Multiply and Add Signed Integers with Saturation

The only in-kernel usage of this is kvm passthrough. The CPU feature
flag is shown as "avx_vnni" in /proc/cpuinfo.

This instruction is currently documented in the latest "extensions"
manual (ISE). It will appear in the "main" manual (SDM) in the future.

Signed-off-by: Kyung Min Park <kyung.min.park@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
---
 arch/x86/include/asm/cpufeatures.h | 1 +
 1 file changed, 1 insertion(+)

Comments

Paolo Bonzini Jan. 5, 2021, 11:47 a.m. UTC | #1
On 05/01/21 01:49, Yang Zhong wrote:
> From: Kyung Min Park <kyung.min.park@intel.com>
> 
> Add AVX version of the Vector Neural Network (VNNI) Instructions.
> 
> A processor supports AVX VNNI instructions if CPUID.0x07.0x1:EAX[4] is
> present. The following instructions are available when this feature is
> present.
>    1. VPDPBUS: Multiply and Add Unsigned and Signed Bytes
>    2. VPDPBUSDS: Multiply and Add Unsigned and Signed Bytes with Saturation
>    3. VPDPWSSD: Multiply and Add Signed Word Integers
>    4. VPDPWSSDS: Multiply and Add Signed Integers with Saturation
> 
> The only in-kernel usage of this is kvm passthrough. The CPU feature
> flag is shown as "avx_vnni" in /proc/cpuinfo.
> 
> This instruction is currently documented in the latest "extensions"
> manual (ISE). It will appear in the "main" manual (SDM) in the future.
> 
> Signed-off-by: Kyung Min Park <kyung.min.park@intel.com>
> Signed-off-by: Yang Zhong <yang.zhong@intel.com>
> Reviewed-by: Tony Luck <tony.luck@intel.com>
> ---
>   arch/x86/include/asm/cpufeatures.h | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index f5ef2d5b9231..d10d9962bd9b 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -293,6 +293,7 @@
>   #define X86_FEATURE_PER_THREAD_MBA	(11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */
>   
>   /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
> +#define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */
>   #define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
>   
>   /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
> 

Boris, is it possible to have a topic branch for this patch?
Borislav Petkov Jan. 5, 2021, 12:14 p.m. UTC | #2
On Tue, Jan 05, 2021 at 12:47:23PM +0100, Paolo Bonzini wrote:
> On 05/01/21 01:49, Yang Zhong wrote:
> > From: Kyung Min Park <kyung.min.park@intel.com>
> > 
> > Add AVX version of the Vector Neural Network (VNNI) Instructions.
> > 
> > A processor supports AVX VNNI instructions if CPUID.0x07.0x1:EAX[4] is
> > present. The following instructions are available when this feature is
> > present.
> >    1. VPDPBUS: Multiply and Add Unsigned and Signed Bytes
> >    2. VPDPBUSDS: Multiply and Add Unsigned and Signed Bytes with Saturation
> >    3. VPDPWSSD: Multiply and Add Signed Word Integers
> >    4. VPDPWSSDS: Multiply and Add Signed Integers with Saturation
> > 
> > The only in-kernel usage of this is kvm passthrough. The CPU feature
> > flag is shown as "avx_vnni" in /proc/cpuinfo.
> > 
> > This instruction is currently documented in the latest "extensions"
> > manual (ISE). It will appear in the "main" manual (SDM) in the future.
> > 
> > Signed-off-by: Kyung Min Park <kyung.min.park@intel.com>
> > Signed-off-by: Yang Zhong <yang.zhong@intel.com>
> > Reviewed-by: Tony Luck <tony.luck@intel.com>
> > ---
> >   arch/x86/include/asm/cpufeatures.h | 1 +
> >   1 file changed, 1 insertion(+)
> > 
> > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> > index f5ef2d5b9231..d10d9962bd9b 100644
> > --- a/arch/x86/include/asm/cpufeatures.h
> > +++ b/arch/x86/include/asm/cpufeatures.h
> > @@ -293,6 +293,7 @@
> >   #define X86_FEATURE_PER_THREAD_MBA	(11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */
> >   /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
> > +#define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */
> >   #define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
> >   /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
> > 
> 
> Boris, is it possible to have a topic branch for this patch?

Just take it through your tree pls.

Acked-by: Borislav Petkov <bp@suse.de>

Thx.
Yang Zhong Jan. 12, 2021, 2:13 a.m. UTC | #3
On Tue, Jan 05, 2021 at 01:14:56PM +0100, Borislav Petkov wrote:
> On Tue, Jan 05, 2021 at 12:47:23PM +0100, Paolo Bonzini wrote:
> > On 05/01/21 01:49, Yang Zhong wrote:
> > > From: Kyung Min Park <kyung.min.park@intel.com>
> > > 
> > > Add AVX version of the Vector Neural Network (VNNI) Instructions.
> > > 
> > > A processor supports AVX VNNI instructions if CPUID.0x07.0x1:EAX[4] is
> > > present. The following instructions are available when this feature is
> > > present.
> > >    1. VPDPBUS: Multiply and Add Unsigned and Signed Bytes
> > >    2. VPDPBUSDS: Multiply and Add Unsigned and Signed Bytes with Saturation
> > >    3. VPDPWSSD: Multiply and Add Signed Word Integers
> > >    4. VPDPWSSDS: Multiply and Add Signed Integers with Saturation
> > > 
> > > The only in-kernel usage of this is kvm passthrough. The CPU feature
> > > flag is shown as "avx_vnni" in /proc/cpuinfo.
> > > 
> > > This instruction is currently documented in the latest "extensions"
> > > manual (ISE). It will appear in the "main" manual (SDM) in the future.
> > > 
> > > Signed-off-by: Kyung Min Park <kyung.min.park@intel.com>
> > > Signed-off-by: Yang Zhong <yang.zhong@intel.com>
> > > Reviewed-by: Tony Luck <tony.luck@intel.com>
> > > ---
> > >   arch/x86/include/asm/cpufeatures.h | 1 +
> > >   1 file changed, 1 insertion(+)
> > > 
> > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> > > index f5ef2d5b9231..d10d9962bd9b 100644
> > > --- a/arch/x86/include/asm/cpufeatures.h
> > > +++ b/arch/x86/include/asm/cpufeatures.h
> > > @@ -293,6 +293,7 @@
> > >   #define X86_FEATURE_PER_THREAD_MBA	(11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */
> > >   /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
> > > +#define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */
> > >   #define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
> > >   /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
> > > 
> > 
> > Boris, is it possible to have a topic branch for this patch?
> 
> Just take it through your tree pls.
> 
> Acked-by: Borislav Petkov <bp@suse.de>
>
  
  Paolo, Boris has acked this kernel patch, and if i need send new patchset to add this 
  acked-by info ? or kvm tree will directly pull this patchset? thanks.

  Yang  

   
> Thx.
> 
> -- 
> Regards/Gruss,
>     Boris.
> 
> https://people.kernel.org/tglx/notes-about-netiquette
Paolo Bonzini Jan. 13, 2021, 12:54 p.m. UTC | #4
>>> Boris, is it possible to have a topic branch for this patch?
>>
>> Just take it through your tree pls.
>>
>> Acked-by: Borislav Petkov <bp@suse.de>
>>
>    
>    Paolo, Boris has acked this kernel patch, and if i need send new patchset to add this
>    acked-by info ? or kvm tree will directly pull this patchset? thanks.

I'll take care of it shortly.

Paolo
diff mbox series

Patch

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index f5ef2d5b9231..d10d9962bd9b 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -293,6 +293,7 @@ 
 #define X86_FEATURE_PER_THREAD_MBA	(11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
+#define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */
 #define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
 
 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */