| Message ID | 20210113183339.446239-8-angelogioacchino.delregno@somainline.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 3f2bc3856bf175c751736c7323188a401ad10a0d |
| Headers | show |
| Series | Add support for Adreno 508/509/512 | expand |
On Wed, Jan 13, 2021 at 07:33:39PM +0100, AngeloGioacchino Del Regno wrote: > From: Konrad Dybcio <konrad.dybcio@somainline.org> > > Port over the command from downstream to prevent undefined > behaviour. Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> > Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > --- > drivers/gpu/drm/msm/adreno/a5xx.xml.h | 2 ++ > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 3 +++ > 2 files changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a5xx.xml.h b/drivers/gpu/drm/msm/adreno/a5xx.xml.h > index 346cc6ff3a36..7b9fcfe95c04 100644 > --- a/drivers/gpu/drm/msm/adreno/a5xx.xml.h > +++ b/drivers/gpu/drm/msm/adreno/a5xx.xml.h > @@ -2367,6 +2367,8 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val) > > #define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x00000e80 > > +#define REG_A5XX_UCHE_MODE_CNTL 0x00000e81 > + > #define REG_A5XX_UCHE_SVM_CNTL 0x00000e82 > > #define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x00000e87 > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > index 23fc851756de..7e553d3efeb2 100644 > --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > @@ -754,6 +754,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu) > adreno_is_a512(adreno_gpu)) > gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, 0, (1 << 9)); > > + /* Disable UCHE global filter as SP can invalidate/flush independently */ > + gpu_write(gpu, REG_A5XX_UCHE_MODE_CNTL, BIT(29)); > + > /* Enable USE_RETENTION_FLOPS */ > gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x02000000); > > -- > 2.29.2 >
diff --git a/drivers/gpu/drm/msm/adreno/a5xx.xml.h b/drivers/gpu/drm/msm/adreno/a5xx.xml.h index 346cc6ff3a36..7b9fcfe95c04 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a5xx.xml.h @@ -2367,6 +2367,8 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val) #define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x00000e80 +#define REG_A5XX_UCHE_MODE_CNTL 0x00000e81 + #define REG_A5XX_UCHE_SVM_CNTL 0x00000e82 #define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x00000e87 diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 23fc851756de..7e553d3efeb2 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -754,6 +754,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu) adreno_is_a512(adreno_gpu)) gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, 0, (1 << 9)); + /* Disable UCHE global filter as SP can invalidate/flush independently */ + gpu_write(gpu, REG_A5XX_UCHE_MODE_CNTL, BIT(29)); + /* Enable USE_RETENTION_FLOPS */ gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x02000000);