Message ID | 20210116181328.3890849-1-f4bug@amsat.org (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | target/mips: fetch code with translator_ld | expand |
在 2021/1/17 上午2:13, Philippe Mathieu-Daudé 写道: > Similarly to commits ae82adc8e29..7f93879e444, use the > translator_ld*() API introduced in commit 409c1a0bf0f > to fetch the code on the MIPS target. > > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > --- > target/mips/tlb_helper.c | 16 ++++++++-------- > target/mips/translate.c | 20 ++++++++++---------- > 2 files changed, 18 insertions(+), 18 deletions(-) > > diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c > index 082c17928d3..f855453ca4d 100644 > --- a/target/mips/tlb_helper.c > +++ b/target/mips/tlb_helper.c > @@ -21,7 +21,7 @@ > #include "cpu.h" > #include "internal.h" > #include "exec/exec-all.h" > -#include "exec/cpu_ldst.h" > +#include "exec/translator.h" > #include "exec/log.h" > #include "hw/mips/cpudevs.h" > > @@ -526,9 +526,9 @@ static bool get_pte(CPUMIPSState *env, uint64_t vaddr, int entry_size, > return false; > } > if (entry_size == 64) { > - *pte = cpu_ldq_code(env, vaddr); > + *pte = translator_ldq(env, vaddr); > } else { > - *pte = cpu_ldl_code(env, vaddr); > + *pte = translator_ldl(env, vaddr); > } > return true; > } > @@ -941,14 +941,14 @@ static inline void set_badinstr_registers(CPUMIPSState *env) > { > if (env->insn_flags & ISA_NANOMIPS32) { > if (env->CP0_Config3 & (1 << CP0C3_BI)) { > - uint32_t instr = (cpu_lduw_code(env, env->active_tc.PC)) << 16; > + uint32_t instr = (translator_lduw(env, env->active_tc.PC)) << 16; > if ((instr & 0x10000000) == 0) { > - instr |= cpu_lduw_code(env, env->active_tc.PC + 2); > + instr |= translator_lduw(env, env->active_tc.PC + 2); > } > env->CP0_BadInstr = instr; > > if ((instr & 0xFC000000) == 0x60000000) { > - instr = cpu_lduw_code(env, env->active_tc.PC + 4) << 16; > + instr = translator_lduw(env, env->active_tc.PC + 4) << 16; > env->CP0_BadInstrX = instr; > } > } > @@ -960,11 +960,11 @@ static inline void set_badinstr_registers(CPUMIPSState *env) > return; > } > if (env->CP0_Config3 & (1 << CP0C3_BI)) { > - env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC); > + env->CP0_BadInstr = translator_ldl(env, env->active_tc.PC); > } > if ((env->CP0_Config3 & (1 << CP0C3_BP)) && > (env->hflags & MIPS_HFLAG_BMASK)) { > - env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4); > + env->CP0_BadInstrP = translator_ldl(env, env->active_tc.PC - 4); > } > } > > diff --git a/target/mips/translate.c b/target/mips/translate.c > index a5cf1742a8b..a6e835809aa 100644 > --- a/target/mips/translate.c > +++ b/target/mips/translate.c > @@ -26,7 +26,7 @@ > #include "cpu.h" > #include "internal.h" > #include "tcg/tcg-op.h" > -#include "exec/cpu_ldst.h" > +#include "exec/translator.h" > #include "exec/helper-proto.h" > #include "exec/helper-gen.h" > #include "hw/semihosting/semihost.h" > @@ -13911,7 +13911,7 @@ static void decode_i64_mips16(DisasContext *ctx, > > static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx) > { > - int extend = cpu_lduw_code(env, ctx->base.pc_next + 2); > + int extend = translator_lduw(env, ctx->base.pc_next + 2); > int op, rx, ry, funct, sa; > int16_t imm, offset; > > @@ -14161,7 +14161,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx) > /* No delay slot, so just process as a normal instruction */ > break; > case M16_OPC_JAL: > - offset = cpu_lduw_code(env, ctx->base.pc_next + 2); > + offset = translator_lduw(env, ctx->base.pc_next + 2); > offset = (((ctx->opcode & 0x1f) << 21) > | ((ctx->opcode >> 5) & 0x1f) << 16 > | offset) << 2; > @@ -16295,7 +16295,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) > uint32_t op, minor, minor2, mips32_op; > uint32_t cond, fmt, cc; > > - insn = cpu_lduw_code(env, ctx->base.pc_next + 2); > + insn = translator_lduw(env, ctx->base.pc_next + 2); > ctx->opcode = (ctx->opcode << 16) | insn; > > rt = (ctx->opcode >> 21) & 0x1f; > @@ -21350,7 +21350,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) > int offset; > int imm; > > - insn = cpu_lduw_code(env, ctx->base.pc_next + 2); > + insn = translator_lduw(env, ctx->base.pc_next + 2); > ctx->opcode = (ctx->opcode << 16) | insn; > > rt = extract32(ctx->opcode, 21, 5); > @@ -21469,7 +21469,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) > break; > case NM_P48I: > { > - insn = cpu_lduw_code(env, ctx->base.pc_next + 4); > + insn = translator_lduw(env, ctx->base.pc_next + 4); > target_long addr_off = extract32(ctx->opcode, 0, 16) | insn << 16; > switch (extract32(ctx->opcode, 16, 5)) { > case NM_LI48: > @@ -29087,17 +29087,17 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) > > is_slot = ctx->hflags & MIPS_HFLAG_BMASK; > if (ctx->insn_flags & ISA_NANOMIPS32) { > - ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next); > + ctx->opcode = translator_lduw(env, ctx->base.pc_next); > insn_bytes = decode_nanomips_opc(env, ctx); > } else if (!(ctx->hflags & MIPS_HFLAG_M16)) { > - ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); > + ctx->opcode = translator_ldl(env, ctx->base.pc_next); > insn_bytes = 4; > decode_opc(env, ctx); > } else if (ctx->insn_flags & ASE_MICROMIPS) { > - ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next); > + ctx->opcode = translator_lduw(env, ctx->base.pc_next); > insn_bytes = decode_micromips_opc(env, ctx); > } else if (ctx->insn_flags & ASE_MIPS16) { > - ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next); > + ctx->opcode = translator_lduw(env, ctx->base.pc_next); > insn_bytes = decode_mips16_opc(env, ctx); > } else { > gen_reserved_instruction(ctx);
On 1/16/21 8:13 AM, Philippe Mathieu-Daudé wrote: > +++ b/target/mips/tlb_helper.c > @@ -21,7 +21,7 @@ > #include "cpu.h" > #include "internal.h" > #include "exec/exec-all.h" > -#include "exec/cpu_ldst.h" > +#include "exec/translator.h" > #include "exec/log.h" > #include "hw/mips/cpudevs.h" > > @@ -526,9 +526,9 @@ static bool get_pte(CPUMIPSState *env, uint64_t vaddr, int entry_size, > return false; > } > if (entry_size == 64) { > - *pte = cpu_ldq_code(env, vaddr); > + *pte = translator_ldq(env, vaddr); > } else { > - *pte = cpu_ldl_code(env, vaddr); > + *pte = translator_ldl(env, vaddr); > } > return true; > } NACK. This is not within the translator. r~
On 1/18/21 6:40 PM, Richard Henderson wrote: > On 1/16/21 8:13 AM, Philippe Mathieu-Daudé wrote: >> +++ b/target/mips/tlb_helper.c >> @@ -21,7 +21,7 @@ >> #include "cpu.h" >> #include "internal.h" >> #include "exec/exec-all.h" >> -#include "exec/cpu_ldst.h" >> +#include "exec/translator.h" >> #include "exec/log.h" >> #include "hw/mips/cpudevs.h" >> >> @@ -526,9 +526,9 @@ static bool get_pte(CPUMIPSState *env, uint64_t vaddr, int entry_size, >> return false; >> } >> if (entry_size == 64) { >> - *pte = cpu_ldq_code(env, vaddr); >> + *pte = translator_ldq(env, vaddr); >> } else { >> - *pte = cpu_ldl_code(env, vaddr); >> + *pte = translator_ldl(env, vaddr); >> } >> return true; >> } > > NACK. This is not within the translator. Oops... Thanks for catching this mistake, Phil.
diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index 082c17928d3..f855453ca4d 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "internal.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "exec/translator.h" #include "exec/log.h" #include "hw/mips/cpudevs.h" @@ -526,9 +526,9 @@ static bool get_pte(CPUMIPSState *env, uint64_t vaddr, int entry_size, return false; } if (entry_size == 64) { - *pte = cpu_ldq_code(env, vaddr); + *pte = translator_ldq(env, vaddr); } else { - *pte = cpu_ldl_code(env, vaddr); + *pte = translator_ldl(env, vaddr); } return true; } @@ -941,14 +941,14 @@ static inline void set_badinstr_registers(CPUMIPSState *env) { if (env->insn_flags & ISA_NANOMIPS32) { if (env->CP0_Config3 & (1 << CP0C3_BI)) { - uint32_t instr = (cpu_lduw_code(env, env->active_tc.PC)) << 16; + uint32_t instr = (translator_lduw(env, env->active_tc.PC)) << 16; if ((instr & 0x10000000) == 0) { - instr |= cpu_lduw_code(env, env->active_tc.PC + 2); + instr |= translator_lduw(env, env->active_tc.PC + 2); } env->CP0_BadInstr = instr; if ((instr & 0xFC000000) == 0x60000000) { - instr = cpu_lduw_code(env, env->active_tc.PC + 4) << 16; + instr = translator_lduw(env, env->active_tc.PC + 4) << 16; env->CP0_BadInstrX = instr; } } @@ -960,11 +960,11 @@ static inline void set_badinstr_registers(CPUMIPSState *env) return; } if (env->CP0_Config3 & (1 << CP0C3_BI)) { - env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC); + env->CP0_BadInstr = translator_ldl(env, env->active_tc.PC); } if ((env->CP0_Config3 & (1 << CP0C3_BP)) && (env->hflags & MIPS_HFLAG_BMASK)) { - env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4); + env->CP0_BadInstrP = translator_ldl(env, env->active_tc.PC - 4); } } diff --git a/target/mips/translate.c b/target/mips/translate.c index a5cf1742a8b..a6e835809aa 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -26,7 +26,7 @@ #include "cpu.h" #include "internal.h" #include "tcg/tcg-op.h" -#include "exec/cpu_ldst.h" +#include "exec/translator.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" #include "hw/semihosting/semihost.h" @@ -13911,7 +13911,7 @@ static void decode_i64_mips16(DisasContext *ctx, static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx) { - int extend = cpu_lduw_code(env, ctx->base.pc_next + 2); + int extend = translator_lduw(env, ctx->base.pc_next + 2); int op, rx, ry, funct, sa; int16_t imm, offset; @@ -14161,7 +14161,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx) /* No delay slot, so just process as a normal instruction */ break; case M16_OPC_JAL: - offset = cpu_lduw_code(env, ctx->base.pc_next + 2); + offset = translator_lduw(env, ctx->base.pc_next + 2); offset = (((ctx->opcode & 0x1f) << 21) | ((ctx->opcode >> 5) & 0x1f) << 16 | offset) << 2; @@ -16295,7 +16295,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) uint32_t op, minor, minor2, mips32_op; uint32_t cond, fmt, cc; - insn = cpu_lduw_code(env, ctx->base.pc_next + 2); + insn = translator_lduw(env, ctx->base.pc_next + 2); ctx->opcode = (ctx->opcode << 16) | insn; rt = (ctx->opcode >> 21) & 0x1f; @@ -21350,7 +21350,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) int offset; int imm; - insn = cpu_lduw_code(env, ctx->base.pc_next + 2); + insn = translator_lduw(env, ctx->base.pc_next + 2); ctx->opcode = (ctx->opcode << 16) | insn; rt = extract32(ctx->opcode, 21, 5); @@ -21469,7 +21469,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) break; case NM_P48I: { - insn = cpu_lduw_code(env, ctx->base.pc_next + 4); + insn = translator_lduw(env, ctx->base.pc_next + 4); target_long addr_off = extract32(ctx->opcode, 0, 16) | insn << 16; switch (extract32(ctx->opcode, 16, 5)) { case NM_LI48: @@ -29087,17 +29087,17 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) is_slot = ctx->hflags & MIPS_HFLAG_BMASK; if (ctx->insn_flags & ISA_NANOMIPS32) { - ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next); + ctx->opcode = translator_lduw(env, ctx->base.pc_next); insn_bytes = decode_nanomips_opc(env, ctx); } else if (!(ctx->hflags & MIPS_HFLAG_M16)) { - ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); + ctx->opcode = translator_ldl(env, ctx->base.pc_next); insn_bytes = 4; decode_opc(env, ctx); } else if (ctx->insn_flags & ASE_MICROMIPS) { - ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next); + ctx->opcode = translator_lduw(env, ctx->base.pc_next); insn_bytes = decode_micromips_opc(env, ctx); } else if (ctx->insn_flags & ASE_MIPS16) { - ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next); + ctx->opcode = translator_lduw(env, ctx->base.pc_next); insn_bytes = decode_mips16_opc(env, ctx); } else { gen_reserved_instruction(ctx);
Similarly to commits ae82adc8e29..7f93879e444, use the translator_ld*() API introduced in commit 409c1a0bf0f to fetch the code on the MIPS target. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- target/mips/tlb_helper.c | 16 ++++++++-------- target/mips/translate.c | 20 ++++++++++---------- 2 files changed, 18 insertions(+), 18 deletions(-)