| Message ID | 20210113014105.28110-2-koba.ko@canonical.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] drm/dp_mst: Retrieve extended DPCD caps for topology manager | expand |
On Wed, 13 Jan 2021, Koba Ko <koba.ko@canonical.com> wrote: > After read the link rate from MST hub, align with > maximum source rate. > > Signed-off-by: Koba Ko <koba.ko@canonical.com> > --- > drivers/gpu/drm/drm_dp_mst_topology.c | 8 ++++++++ > drivers/gpu/drm/i915/display/intel_dp.c | 7 +++++++ > include/drm/drm_dp_helper.h | 8 ++++++++ > include/drm/drm_dp_mst_helper.h | 4 ++++ > 4 files changed, 27 insertions(+) > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c > index 6982ecbf30b5..e7ceae97be85 100644 > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > @@ -3672,6 +3672,10 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms > { > int ret = 0; > struct drm_dp_mst_branch *mstb = NULL; > + unsigned int max_link_rate_tbl[MAX_DRM_DP_MAX_RATE + 1] = { > + DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4, > + DP_LINK_BW_8_1, DP_LINK_RATE_TABLE > + }; Please no. Read on for why. > > mutex_lock(&mgr->payload_lock); > mutex_lock(&mgr->lock); > @@ -3693,6 +3697,9 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms > goto out_unlock; > } > > + if (mgr->max_source_rate < MAX_DRM_DP_MAX_RATE) > + mgr->dpcd[1] = max_link_rate_tbl[mgr->max_source_rate]; Make ->max_source_rate the actual physical rate in kHz, and use drm_dp_link_rate_to_bw_code() here. > + > mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr->dpcd[1], > mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK); > if (mgr->pbn_div == 0) { > @@ -5422,6 +5429,7 @@ int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, > mgr->aux = aux; > mgr->max_dpcd_transaction_bytes = max_dpcd_transaction_bytes; > mgr->max_payloads = max_payloads; > + mgr->max_source_rate = MAX_DRM_DP_MAX_RATE; > mgr->conn_base_id = conn_base_id; > if (max_payloads + 1 > sizeof(mgr->payload_mask) * 8 || > max_payloads + 1 > sizeof(mgr->vcpi_mask) * 8) > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 469e765a1b7b..a89b4c823123 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -5392,6 +5392,13 @@ intel_dp_configure_mst(struct intel_dp *intel_dp) > intel_dp->is_mst = sink_can_mst && > i915->params.enable_dp_mst; > > + if (intel_dp_source_supports_hbr3(intel_dp)) > + intel_dp->mst_mgr.max_source_rate = DRM_DP_MAX_RATE_HBR3; > + else if (intel_dp_source_supports_hbr2(intel_dp)) > + intel_dp->mst_mgr.max_source_rate = DRM_DP_MAX_RATE_HBR2; > + else > + intel_dp->mst_mgr.max_source_rate = DRM_DP_MAX_RATE_HBR; Whenever this file references a "rate", it's the rate in kHz. This is confusing. Use the rate in kHz. Also, please look at how intel_dp_source_supports_hbr* are implemented; we already have all the supported source rates cached in intel_dp. The max source rate is: intel_dp->source_rates[intel_dp->num_source_rates - 1]. No need to do the if ladder here at all. If you like, you can add a helper: int intel_dp_max_source_rate(struct intel_dp *intel_dp) { return intel_dp->source_rates[intel_dp->num_source_rates - 1]; } and reuse that in the supports_hbr* functions: bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) { return intel_dp_max_source_rate(intel_dp) >= 540000; } > + > drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, > intel_dp->is_mst); > } > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index 6236f212da61..ef2b328469cd 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -183,6 +183,14 @@ struct drm_device; > #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ > # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ > > +enum drm_dp_max_link_rate { > + DRM_DP_MAX_RATE_RBR = 0, > + DRM_DP_MAX_RATE_HBR, > + DRM_DP_MAX_RATE_HBR2, > + DRM_DP_MAX_RATE_HBR3, > + MAX_DRM_DP_MAX_RATE > +}; We already have 1) actual physical rates, in kHz, and 2) the DPCD rate codes, such as DP_LINK_BW_1_62. Do *not* add a third representation. Prefer kHz throughout, and convert to/from the DPCD codes near where they are needed. > + > /* Multiple stream transport */ > #define DP_FAUX_CAP 0x020 /* 1.2 */ > # define DP_FAUX_CAP_1 (1 << 0) > diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h > index f5e92fe9151c..e7d8c899fea0 100644 > --- a/include/drm/drm_dp_mst_helper.h > +++ b/include/drm/drm_dp_mst_helper.h > @@ -593,6 +593,10 @@ struct drm_dp_mst_topology_mgr { > * @max_payloads: maximum number of payloads the GPU can generate. > */ > int max_payloads; > + /** > + * @max_source_rate: maximum link rate of source. > + */ > + int max_source_rate; Again, make this the actual rate in kHz. That's what I'd think it is by reading the comment above anyway. > /** > * @conn_base_id: DRM connector ID this mgr is connected to. Only used > * to build the MST connector path value.
On Wed, Jan 13, 2021 at 7:51 PM Jani Nikula <jani.nikula@linux.intel.com> wrote: > > On Wed, 13 Jan 2021, Koba Ko <koba.ko@canonical.com> wrote: > > After read the link rate from MST hub, align with > > maximum source rate. > > > > Signed-off-by: Koba Ko <koba.ko@canonical.com> > > --- > > drivers/gpu/drm/drm_dp_mst_topology.c | 8 ++++++++ > > drivers/gpu/drm/i915/display/intel_dp.c | 7 +++++++ > > include/drm/drm_dp_helper.h | 8 ++++++++ > > include/drm/drm_dp_mst_helper.h | 4 ++++ > > 4 files changed, 27 insertions(+) > > > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c > > index 6982ecbf30b5..e7ceae97be85 100644 > > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > > @@ -3672,6 +3672,10 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms > > { > > int ret = 0; > > struct drm_dp_mst_branch *mstb = NULL; > > + unsigned int max_link_rate_tbl[MAX_DRM_DP_MAX_RATE + 1] = { > > + DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4, > > + DP_LINK_BW_8_1, DP_LINK_RATE_TABLE > > + }; > > Please no. Read on for why. > > > > > mutex_lock(&mgr->payload_lock); > > mutex_lock(&mgr->lock); > > @@ -3693,6 +3697,9 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms > > goto out_unlock; > > } > > > > + if (mgr->max_source_rate < MAX_DRM_DP_MAX_RATE) > > + mgr->dpcd[1] = max_link_rate_tbl[mgr->max_source_rate]; > > Make ->max_source_rate the actual physical rate in kHz, and use > drm_dp_link_rate_to_bw_code() here. > > > + > > mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr->dpcd[1], > > mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK); > > if (mgr->pbn_div == 0) { > > @@ -5422,6 +5429,7 @@ int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, > > mgr->aux = aux; > > mgr->max_dpcd_transaction_bytes = max_dpcd_transaction_bytes; > > mgr->max_payloads = max_payloads; > > + mgr->max_source_rate = MAX_DRM_DP_MAX_RATE; > > mgr->conn_base_id = conn_base_id; > > if (max_payloads + 1 > sizeof(mgr->payload_mask) * 8 || > > max_payloads + 1 > sizeof(mgr->vcpi_mask) * 8) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > > index 469e765a1b7b..a89b4c823123 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -5392,6 +5392,13 @@ intel_dp_configure_mst(struct intel_dp *intel_dp) > > intel_dp->is_mst = sink_can_mst && > > i915->params.enable_dp_mst; > > > > + if (intel_dp_source_supports_hbr3(intel_dp)) > > + intel_dp->mst_mgr.max_source_rate = DRM_DP_MAX_RATE_HBR3; > > + else if (intel_dp_source_supports_hbr2(intel_dp)) > > + intel_dp->mst_mgr.max_source_rate = DRM_DP_MAX_RATE_HBR2; > > + else > > + intel_dp->mst_mgr.max_source_rate = DRM_DP_MAX_RATE_HBR; > > Whenever this file references a "rate", it's the rate in kHz. This is > confusing. Use the rate in kHz. > > Also, please look at how intel_dp_source_supports_hbr* are implemented; > we already have all the supported source rates cached in intel_dp. > > The max source rate is: > > intel_dp->source_rates[intel_dp->num_source_rates - 1]. > > No need to do the if ladder here at all. If you like, you can add a > helper: > > int intel_dp_max_source_rate(struct intel_dp *intel_dp) > { > return intel_dp->source_rates[intel_dp->num_source_rates - 1]; > } > > and reuse that in the supports_hbr* functions: > > bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) > { > return intel_dp_max_source_rate(intel_dp) >= 540000; > } > > > + > > drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, > > intel_dp->is_mst); > > } > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > > index 6236f212da61..ef2b328469cd 100644 > > --- a/include/drm/drm_dp_helper.h > > +++ b/include/drm/drm_dp_helper.h > > @@ -183,6 +183,14 @@ struct drm_device; > > #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ > > # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ > > > > +enum drm_dp_max_link_rate { > > + DRM_DP_MAX_RATE_RBR = 0, > > + DRM_DP_MAX_RATE_HBR, > > + DRM_DP_MAX_RATE_HBR2, > > + DRM_DP_MAX_RATE_HBR3, > > + MAX_DRM_DP_MAX_RATE > > +}; > > We already have 1) actual physical rates, in kHz, and 2) the DPCD rate > codes, such as DP_LINK_BW_1_62. > > Do *not* add a third representation. Prefer kHz throughout, and convert > to/from the DPCD codes near where they are needed. > > > + > > /* Multiple stream transport */ > > #define DP_FAUX_CAP 0x020 /* 1.2 */ > > # define DP_FAUX_CAP_1 (1 << 0) > > diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h > > index f5e92fe9151c..e7d8c899fea0 100644 > > --- a/include/drm/drm_dp_mst_helper.h > > +++ b/include/drm/drm_dp_mst_helper.h > > @@ -593,6 +593,10 @@ struct drm_dp_mst_topology_mgr { > > * @max_payloads: maximum number of payloads the GPU can generate. > > */ > > int max_payloads; > > + /** > > + * @max_source_rate: maximum link rate of source. > > + */ > > + int max_source_rate; > > Again, make this the actual rate in kHz. That's what I'd think it is by > reading the comment above anyway. > > > /** > > * @conn_base_id: DRM connector ID this mgr is connected to. Only used > > * to build the MST connector path value. > > -- > Jani Nikula, Intel Open Source Graphics Center Hi Jani, thanks and will send the v2 according to the suggestions. Thanks *Koba Ko*
On Wed, Jan 13, 2021 at 01:51:00PM +0200, Jani Nikula wrote: > On Wed, 13 Jan 2021, Koba Ko <koba.ko@canonical.com> wrote: > > After read the link rate from MST hub, align with > > maximum source rate. > > > > Signed-off-by: Koba Ko <koba.ko@canonical.com> > > --- > > drivers/gpu/drm/drm_dp_mst_topology.c | 8 ++++++++ > > drivers/gpu/drm/i915/display/intel_dp.c | 7 +++++++ > > include/drm/drm_dp_helper.h | 8 ++++++++ > > include/drm/drm_dp_mst_helper.h | 4 ++++ > > 4 files changed, 27 insertions(+) > > > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c > > index 6982ecbf30b5..e7ceae97be85 100644 > > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > > @@ -3672,6 +3672,10 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms > > { > > int ret = 0; > > struct drm_dp_mst_branch *mstb = NULL; > > + unsigned int max_link_rate_tbl[MAX_DRM_DP_MAX_RATE + 1] = { > > + DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4, > > + DP_LINK_BW_8_1, DP_LINK_RATE_TABLE > > + }; > > Please no. Read on for why. > > > > > mutex_lock(&mgr->payload_lock); > > mutex_lock(&mgr->lock); > > @@ -3693,6 +3697,9 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms > > goto out_unlock; > > } > > > > + if (mgr->max_source_rate < MAX_DRM_DP_MAX_RATE) > > + mgr->dpcd[1] = max_link_rate_tbl[mgr->max_source_rate]; > > Make ->max_source_rate the actual physical rate in kHz, and use > drm_dp_link_rate_to_bw_code() here. > > > + > > mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr->dpcd[1], > > mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK); > > if (mgr->pbn_div == 0) { > > @@ -5422,6 +5429,7 @@ int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, > > mgr->aux = aux; > > mgr->max_dpcd_transaction_bytes = max_dpcd_transaction_bytes; > > mgr->max_payloads = max_payloads; > > + mgr->max_source_rate = MAX_DRM_DP_MAX_RATE; > > mgr->conn_base_id = conn_base_id; > > if (max_payloads + 1 > sizeof(mgr->payload_mask) * 8 || > > max_payloads + 1 > sizeof(mgr->vcpi_mask) * 8) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > > index 469e765a1b7b..a89b4c823123 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -5392,6 +5392,13 @@ intel_dp_configure_mst(struct intel_dp *intel_dp) > > intel_dp->is_mst = sink_can_mst && > > i915->params.enable_dp_mst; > > > > + if (intel_dp_source_supports_hbr3(intel_dp)) > > + intel_dp->mst_mgr.max_source_rate = DRM_DP_MAX_RATE_HBR3; > > + else if (intel_dp_source_supports_hbr2(intel_dp)) > > + intel_dp->mst_mgr.max_source_rate = DRM_DP_MAX_RATE_HBR2; > > + else > > + intel_dp->mst_mgr.max_source_rate = DRM_DP_MAX_RATE_HBR; > > Whenever this file references a "rate", it's the rate in kHz. This is > confusing. Use the rate in kHz. > > Also, please look at how intel_dp_source_supports_hbr* are implemented; > we already have all the supported source rates cached in intel_dp. > > The max source rate is: > > intel_dp->source_rates[intel_dp->num_source_rates - 1]. > > No need to do the if ladder here at all. If you like, you can add a > helper: > > int intel_dp_max_source_rate(struct intel_dp *intel_dp) > { > return intel_dp->source_rates[intel_dp->num_source_rates - 1]; > } Using the max source rate isn't super great either. A bit better than the current mess though. The correct fix would be to let the driver provide the actually used link_rate+lane_count to the MST code during atomic_check(), instead of trying to guess what the driver is going to use.
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 6982ecbf30b5..e7ceae97be85 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -3672,6 +3672,10 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms { int ret = 0; struct drm_dp_mst_branch *mstb = NULL; + unsigned int max_link_rate_tbl[MAX_DRM_DP_MAX_RATE + 1] = { + DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4, + DP_LINK_BW_8_1, DP_LINK_RATE_TABLE + }; mutex_lock(&mgr->payload_lock); mutex_lock(&mgr->lock); @@ -3693,6 +3697,9 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms goto out_unlock; } + if (mgr->max_source_rate < MAX_DRM_DP_MAX_RATE) + mgr->dpcd[1] = max_link_rate_tbl[mgr->max_source_rate]; + mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr->dpcd[1], mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK); if (mgr->pbn_div == 0) { @@ -5422,6 +5429,7 @@ int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, mgr->aux = aux; mgr->max_dpcd_transaction_bytes = max_dpcd_transaction_bytes; mgr->max_payloads = max_payloads; + mgr->max_source_rate = MAX_DRM_DP_MAX_RATE; mgr->conn_base_id = conn_base_id; if (max_payloads + 1 > sizeof(mgr->payload_mask) * 8 || max_payloads + 1 > sizeof(mgr->vcpi_mask) * 8) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 469e765a1b7b..a89b4c823123 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5392,6 +5392,13 @@ intel_dp_configure_mst(struct intel_dp *intel_dp) intel_dp->is_mst = sink_can_mst && i915->params.enable_dp_mst; + if (intel_dp_source_supports_hbr3(intel_dp)) + intel_dp->mst_mgr.max_source_rate = DRM_DP_MAX_RATE_HBR3; + else if (intel_dp_source_supports_hbr2(intel_dp)) + intel_dp->mst_mgr.max_source_rate = DRM_DP_MAX_RATE_HBR2; + else + intel_dp->mst_mgr.max_source_rate = DRM_DP_MAX_RATE_HBR; + drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); } diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 6236f212da61..ef2b328469cd 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -183,6 +183,14 @@ struct drm_device; #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ +enum drm_dp_max_link_rate { + DRM_DP_MAX_RATE_RBR = 0, + DRM_DP_MAX_RATE_HBR, + DRM_DP_MAX_RATE_HBR2, + DRM_DP_MAX_RATE_HBR3, + MAX_DRM_DP_MAX_RATE +}; + /* Multiple stream transport */ #define DP_FAUX_CAP 0x020 /* 1.2 */ # define DP_FAUX_CAP_1 (1 << 0) diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h index f5e92fe9151c..e7d8c899fea0 100644 --- a/include/drm/drm_dp_mst_helper.h +++ b/include/drm/drm_dp_mst_helper.h @@ -593,6 +593,10 @@ struct drm_dp_mst_topology_mgr { * @max_payloads: maximum number of payloads the GPU can generate. */ int max_payloads; + /** + * @max_source_rate: maximum link rate of source. + */ + int max_source_rate; /** * @conn_base_id: DRM connector ID this mgr is connected to. Only used * to build the MST connector path value.
After read the link rate from MST hub, align with maximum source rate. Signed-off-by: Koba Ko <koba.ko@canonical.com> --- drivers/gpu/drm/drm_dp_mst_topology.c | 8 ++++++++ drivers/gpu/drm/i915/display/intel_dp.c | 7 +++++++ include/drm/drm_dp_helper.h | 8 ++++++++ include/drm/drm_dp_mst_helper.h | 4 ++++ 4 files changed, 27 insertions(+)