| Message ID | 20210124135610.1779295-1-iskren.chernev@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/4] ARM: dts: qcom: msm8974: add gpu support | expand |
Hi, > + gpu_opp_table: opp_table { > + status = "disabled"; Is there a good reason to disable this? > + opp-800000000 { > + opp-hz = /bits/ 64 <800000000>; > + }; No. A330 can't go lightspeed (unless there's some secret ultra-binned msm8974pro-v4-ad-5g). [1] > + > + opp-500000000 { > + opp-hz = /bits/ 64 <500000000>; > + }; > + > + opp-275000000 { > + opp-hz = /bits/ 64 <275000000>; > + }; > + }; IMHO we should create separate DTs for all revisions of 8974 (sigh) and keep the opp tables in there, only leaving a lowest-common-denominator one here (which according to downstream and the msm/drm driver would be 27000000 /27MHz/) to make it at least probe for everybody.. On a note, max GPU frequencies (based on [1] and grepping for gpu-pwrlevels or qcom,gpu-freq downstream) are: * 578 MHz for PRO (so -AC) * 550 MHz is mentioned in [1] but not downstream.. * 450 MHz for everything else (v2.2 has more DVFS steps) > + // iommus = <&gpu_iommu 0>; I *think* you're going to need more gpu contexts (user/priv/spare), but don't quote me on that. Konrad [1] https://www.anandtech.com/show/7846/the-difference-between-snapdragon-800-and-801-clearing-up-confusion
On Sun 2021-01-24 15:56:07, Iskren Chernev wrote: > From: Brian Masney <masneyb@onstation.org> > > Add support for the a3xx GPU This is phone, right? Can I ask phone-devel@vger.kernel.org to be cc-ed? Thank you, Pavel
On Sun, Jan 24, 2021 at 03:56:06PM +0100, Konrad Dybcio wrote: > Hi, > > > > + gpu_opp_table: opp_table { > > + status = "disabled"; > > > Is there a good reason to disable this? > > > > + opp-800000000 { > > + opp-hz = /bits/ 64 <800000000>; > > + }; > > No. A330 can't go lightspeed (unless there's some secret ultra-binned msm8974pro-v4-ad-5g). [1] Hi Iskren, I believe that the Nexus 5 GPU frequencies are documented in the downstream kernel at: https://github.com/AICP/kernel_lge_hammerhead/blob/n7.1/arch/arm/boot/dts/msm8974-gpu.dtsi#L67 I am fairly certain that the qcom,bus-freq property is an index into the qcom,msm-bus,vectors-KBps property above. This will map to the interconnect and operating points in the upstream kernel. Note that the actual implementation in a3xx_gpu.c and a4xx_gpu.c currently has this snippet to set the bus speed: /* * Set the ICC path to maximum speed for now by multiplying the fastest * frequency by the bus width (8). We'll want to scale this later on to * improve battery life. */ icc_set_bw(icc_path, 0, Bps_to_icc(gpu->fast_rate) * 8); icc_set_bw(ocmem_icc_path, 0, Bps_to_icc(gpu->fast_rate) * 8); This should be fine for the time being. You'll want to document it correctly in device tree though. If the v2 changes too much, then feel free to drop my name from the patch. I thought that I had made these changes already but apparently not. :/ Brian
On 1/24/21 11:05 PM, Pavel Machek wrote: > On Sun 2021-01-24 15:56:07, Iskren Chernev wrote: >> From: Brian Masney <masneyb@onstation.org> >> >> Add support for the a3xx GPU > > This is phone, right? Can I ask phone-devel@vger.kernel.org to be > cc-ed? CC-ing phone-devel@vger.kernel.org. I'm not sure why you didn't do it :-/ > > Thank you, > Pavel > > Regards, Iskren
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 51f5f904f9eb9..c399446d8154e 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1399,6 +1399,51 @@ cnoc: interconnect@fc480000 { <&rpmcc RPM_SMD_CNOC_A_CLK>; }; + gpu_opp_table: opp_table { + status = "disabled"; + + compatible = "operating-points-v2"; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + }; + + opp-275000000 { + opp-hz = /bits/ 64 <275000000>; + }; + }; + + gpu: adreno@fdb00000 { + status = "disabled"; + + compatible = "qcom,adreno-330.2", + "qcom,adreno"; + reg = <0xfdb00000 0x10000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + clock-names = "core", + "iface", + "mem_iface"; + clocks = <&mmcc OXILI_GFX3D_CLK>, + <&mmcc OXILICX_AHB_CLK>, + <&mmcc OXILICX_AXI_CLK>; + sram = <&gmu_sram>; + power-domains = <&mmcc OXILICX_GDSC>; + operating-points-v2 = <&gpu_opp_table>; + + interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>, + <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>; + interconnect-names = "gfx-mem", + "ocmem"; + + // iommus = <&gpu_iommu 0>; + }; + mdss: mdss@fd900000 { status = "disabled";