| Message ID | 20210114221059.483390-1-angelogioacchino.delregno@somainline.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | Clock fixes for MSM8998 GCC, MMCC, GPUCC | expand |
Il 14/01/21 23:10, AngeloGioacchino Del Regno ha scritto: > This patch series fixes some issues with the MSM8998 clocks and, in > particular, brings a very important fix to the GCC PLLs. > > These fixes are enhancing this SoC's stability and also makes it > possible to eventually enable the Adreno GPU (with proper clock > scaling) and other components. > > This patch series was tested on: > - Sony Xperia XZ Premium (MSM8998) > - F(x)Tec Pro1 (MSM8998) > Forgot to write this part, so adding as a reply to myself... Changes in v2: - Separated dt-bindings headers definitions additions from actual code, as per Rob Herring's review > AngeloGioacchino Del Regno (11): > dt-bindings: clocks: gcc-msm8998: Add GCC_MMSS_GPLL0_CLK definition > clk: qcom: gcc-msm8998: Wire up gcc_mmss_gpll0 clock > dt-bindings: clock: gcc-msm8998: Add HMSS_GPLL0_CLK_SRC definition > clk: qcom: gcc-msm8998: Add missing hmss_gpll0_clk_src clock > clk: qcom: gcc-msm8998: Mark gpu_cfg_ahb_clk as critical > clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLs > clk: qcom: mmcc-msm8998: Set CLK_GET_RATE_NOCACHE to pixel/byte clks > clk: qcom: mmcc-msm8998: Add hardware clockgating registers to some > clks > clk: qcom: mmcc-msm8998: Set bimc_smmu_gdsc always on > clk: qcom: gpucc-msm8998: Add resets, cxc, fix flags on gpu_gx_gdsc > clk: qcom: gpucc-msm8998: Allow fabia gpupll0 rate setting > > drivers/clk/qcom/gcc-msm8998.c | 143 ++++++++++++------- > drivers/clk/qcom/gpucc-msm8998.c | 18 ++- > drivers/clk/qcom/mmcc-msm8998.c | 20 ++- > include/dt-bindings/clock/qcom,gcc-msm8998.h | 2 + > 4 files changed, 125 insertions(+), 58 deletions(-) >
On 14.01.2021 23:10, AngeloGioacchino Del Regno wrote: > This patch series fixes some issues with the MSM8998 clocks and, in > particular, brings a very important fix to the GCC PLLs. > > These fixes are enhancing this SoC's stability and also makes it > possible to eventually enable the Adreno GPU (with proper clock > scaling) and other components. > > This patch series was tested on: > - Sony Xperia XZ Premium (MSM8998) > - F(x)Tec Pro1 (MSM8998) > > AngeloGioacchino Del Regno (11): > dt-bindings: clocks: gcc-msm8998: Add GCC_MMSS_GPLL0_CLK definition > clk: qcom: gcc-msm8998: Wire up gcc_mmss_gpll0 clock > dt-bindings: clock: gcc-msm8998: Add HMSS_GPLL0_CLK_SRC definition > clk: qcom: gcc-msm8998: Add missing hmss_gpll0_clk_src clock > clk: qcom: gcc-msm8998: Mark gpu_cfg_ahb_clk as critical > clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLs > clk: qcom: mmcc-msm8998: Set CLK_GET_RATE_NOCACHE to pixel/byte clks > clk: qcom: mmcc-msm8998: Add hardware clockgating registers to some > clks > clk: qcom: mmcc-msm8998: Set bimc_smmu_gdsc always on > clk: qcom: gpucc-msm8998: Add resets, cxc, fix flags on gpu_gx_gdsc > clk: qcom: gpucc-msm8998: Allow fabia gpupll0 rate setting > > drivers/clk/qcom/gcc-msm8998.c | 143 ++++++++++++------- > drivers/clk/qcom/gpucc-msm8998.c | 18 ++- > drivers/clk/qcom/mmcc-msm8998.c | 20 ++- > include/dt-bindings/clock/qcom,gcc-msm8998.h | 2 + > 4 files changed, 125 insertions(+), 58 deletions(-) Bump! I can tell all of these patches work as they should :)
This patch series fixes some issues with the MSM8998 clocks and, in particular, brings a very important fix to the GCC PLLs. These fixes are enhancing this SoC's stability and also makes it possible to eventually enable the Adreno GPU (with proper clock scaling) and other components. This patch series was tested on: - Sony Xperia XZ Premium (MSM8998) - F(x)Tec Pro1 (MSM8998) AngeloGioacchino Del Regno (11): dt-bindings: clocks: gcc-msm8998: Add GCC_MMSS_GPLL0_CLK definition clk: qcom: gcc-msm8998: Wire up gcc_mmss_gpll0 clock dt-bindings: clock: gcc-msm8998: Add HMSS_GPLL0_CLK_SRC definition clk: qcom: gcc-msm8998: Add missing hmss_gpll0_clk_src clock clk: qcom: gcc-msm8998: Mark gpu_cfg_ahb_clk as critical clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLs clk: qcom: mmcc-msm8998: Set CLK_GET_RATE_NOCACHE to pixel/byte clks clk: qcom: mmcc-msm8998: Add hardware clockgating registers to some clks clk: qcom: mmcc-msm8998: Set bimc_smmu_gdsc always on clk: qcom: gpucc-msm8998: Add resets, cxc, fix flags on gpu_gx_gdsc clk: qcom: gpucc-msm8998: Allow fabia gpupll0 rate setting drivers/clk/qcom/gcc-msm8998.c | 143 ++++++++++++------- drivers/clk/qcom/gpucc-msm8998.c | 18 ++- drivers/clk/qcom/mmcc-msm8998.c | 20 ++- include/dt-bindings/clock/qcom,gcc-msm8998.h | 2 + 4 files changed, 125 insertions(+), 58 deletions(-)