diff mbox series

[net] net: enetc: initialize the RFS and RSS memories

Message ID 20210204134511.2640309-1-vladimir.oltean@nxp.com (mailing list archive)
State Accepted
Commit 07bf34a50e327975b21a9dee64d220c3dcb72ee9
Delegated to: Netdev Maintainers
Headers show
Series [net] net: enetc: initialize the RFS and RSS memories | expand

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Commit Message

Vladimir Oltean Feb. 4, 2021, 1:45 p.m. UTC
Michael tried to enable Advanced Error Reporting through the ENETC's
Root Complex Event Collector, and the system started spitting out single
bit correctable ECC errors coming from the ENETC interfaces:

pcieport 0000:00:1f.0: AER: Multiple Corrected error received: 0000:00:00.0
fsl_enetc 0000:00:00.0: PCIe Bus Error: severity=Corrected, type=Transaction Layer, (Receiver ID)
fsl_enetc 0000:00:00.0:   device [1957:e100] error status/mask=00004000/00000000
fsl_enetc 0000:00:00.0:    [14] CorrIntErr
fsl_enetc 0000:00:00.1: PCIe Bus Error: severity=Corrected, type=Transaction Layer, (Receiver ID)
fsl_enetc 0000:00:00.1:   device [1957:e100] error status/mask=00004000/00000000
fsl_enetc 0000:00:00.1:    [14] CorrIntErr

Further investigating the port correctable memory error detect register
(PCMEDR) shows that these AER errors have an associated SOURCE_ID of 6
(RFS/RSS):

$ devmem 0x1f8010e10 32
0xC0000006
$ devmem 0x1f8050e10 32
0xC0000006

Discussion with the hardware design engineers reveals that on LS1028A,
the hardware does not do initialization of that RFS/RSS memory, and that
software should clear/initialize the entire table before starting to
operate. That comes as a bit of a surprise, since the driver does not do
initialization of the RFS memory. Also, the initialization of the
Receive Side Scaling is done only partially.

Even though the entire ENETC IP has a single shared flow steering
memory, the flow steering service should returns matches only for TCAM
entries that are within the range of the Station Interface that is doing
the search. Therefore, it should be sufficient for a Station Interface
to initialize all of its own entries in order to avoid any ECC errors,
and only the Station Interfaces in use should need initialization.

There are Physical Station Interfaces associated with PCIe PFs and
Virtual Station Interfaces associated with PCIe VFs. We let the PF
driver initialize the entire port's memory, which includes the RFS
entries which are going to be used by the VF.

Reported-by: Michael Walle <michael@walle.cc>
Fixes: d4fd0404c1c9 ("enetc: Introduce basic PF and VF ENETC ethernet drivers")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 .../net/ethernet/freescale/enetc/enetc_hw.h   |  2 +
 .../net/ethernet/freescale/enetc/enetc_pf.c   | 59 +++++++++++++++++++
 2 files changed, 61 insertions(+)

Comments

Michael Walle Feb. 4, 2021, 1:51 p.m. UTC | #1
Am 2021-02-04 14:45, schrieb Vladimir Oltean:
> Michael tried to enable Advanced Error Reporting through the ENETC's
> Root Complex Event Collector, and the system started spitting out 
> single
> bit correctable ECC errors coming from the ENETC interfaces:
> 
> pcieport 0000:00:1f.0: AER: Multiple Corrected error received: 
> 0000:00:00.0
> fsl_enetc 0000:00:00.0: PCIe Bus Error: severity=Corrected,
> type=Transaction Layer, (Receiver ID)
> fsl_enetc 0000:00:00.0:   device [1957:e100] error 
> status/mask=00004000/00000000
> fsl_enetc 0000:00:00.0:    [14] CorrIntErr
> fsl_enetc 0000:00:00.1: PCIe Bus Error: severity=Corrected,
> type=Transaction Layer, (Receiver ID)
> fsl_enetc 0000:00:00.1:   device [1957:e100] error 
> status/mask=00004000/00000000
> fsl_enetc 0000:00:00.1:    [14] CorrIntErr
> 
> Further investigating the port correctable memory error detect register
> (PCMEDR) shows that these AER errors have an associated SOURCE_ID of 6
> (RFS/RSS):
> 
> $ devmem 0x1f8010e10 32
> 0xC0000006
> $ devmem 0x1f8050e10 32
> 0xC0000006
> 
> Discussion with the hardware design engineers reveals that on LS1028A,
> the hardware does not do initialization of that RFS/RSS memory, and 
> that
> software should clear/initialize the entire table before starting to
> operate. That comes as a bit of a surprise, since the driver does not 
> do
> initialization of the RFS memory. Also, the initialization of the
> Receive Side Scaling is done only partially.
> 
> Even though the entire ENETC IP has a single shared flow steering
> memory, the flow steering service should returns matches only for TCAM
> entries that are within the range of the Station Interface that is 
> doing
> the search. Therefore, it should be sufficient for a Station Interface
> to initialize all of its own entries in order to avoid any ECC errors,
> and only the Station Interfaces in use should need initialization.
> 
> There are Physical Station Interfaces associated with PCIe PFs and
> Virtual Station Interfaces associated with PCIe VFs. We let the PF
> driver initialize the entire port's memory, which includes the RFS
> entries which are going to be used by the VF.
> 
> Reported-by: Michael Walle <michael@walle.cc>
> Fixes: d4fd0404c1c9 ("enetc: Introduce basic PF and VF ENETC ethernet 
> drivers")
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>

Tested-by: Michael Walle <michael@walle.cc>

Thanks Vladimir!

-michael
Jesse Brandeburg Feb. 5, 2021, 1:13 a.m. UTC | #2
Vladimir Oltean wrote:
> Discussion with the hardware design engineers reveals that on LS1028A,
> the hardware does not do initialization of that RFS/RSS memory, and that
> software should clear/initialize the entire table before starting to
> operate. That comes as a bit of a surprise, since the driver does not do
> initialization of the RFS memory. Also, the initialization of the
> Receive Side Scaling is done only partially.

...
 
> Reported-by: Michael Walle <michael@walle.cc>
> Fixes: d4fd0404c1c9 ("enetc: Introduce basic PF and VF ENETC ethernet drivers")
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>

Reviewed-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
patchwork-bot+netdevbpf@kernel.org Feb. 5, 2021, 4:40 a.m. UTC | #3
Hello:

This patch was applied to netdev/net.git (refs/heads/master):

On Thu,  4 Feb 2021 15:45:11 +0200 you wrote:
> Michael tried to enable Advanced Error Reporting through the ENETC's
> Root Complex Event Collector, and the system started spitting out single
> bit correctable ECC errors coming from the ENETC interfaces:
> 
> pcieport 0000:00:1f.0: AER: Multiple Corrected error received: 0000:00:00.0
> fsl_enetc 0000:00:00.0: PCIe Bus Error: severity=Corrected, type=Transaction Layer, (Receiver ID)
> fsl_enetc 0000:00:00.0:   device [1957:e100] error status/mask=00004000/00000000
> fsl_enetc 0000:00:00.0:    [14] CorrIntErr
> fsl_enetc 0000:00:00.1: PCIe Bus Error: severity=Corrected, type=Transaction Layer, (Receiver ID)
> fsl_enetc 0000:00:00.1:   device [1957:e100] error status/mask=00004000/00000000
> fsl_enetc 0000:00:00.1:    [14] CorrIntErr
> 
> [...]

Here is the summary with links:
  - [net] net: enetc: initialize the RFS and RSS memories
    https://git.kernel.org/netdev/net/c/07bf34a50e32

You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
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diff mbox series

Patch

diff --git a/drivers/net/ethernet/freescale/enetc/enetc_hw.h b/drivers/net/ethernet/freescale/enetc/enetc_hw.h
index e1e950d48c92..c71fe8d751d5 100644
--- a/drivers/net/ethernet/freescale/enetc/enetc_hw.h
+++ b/drivers/net/ethernet/freescale/enetc/enetc_hw.h
@@ -196,6 +196,8 @@  enum enetc_bdr_type {TX, RX};
 #define ENETC_CBS_BW_MASK	GENMASK(6, 0)
 #define ENETC_PTCCBSR1(n)	(0x1114 + (n) * 8) /* n = 0 to 7*/
 #define ENETC_RSSHASH_KEY_SIZE	40
+#define ENETC_PRSSCAPR		0x1404
+#define ENETC_PRSSCAPR_GET_NUM_RSS(val)	(BIT((val) & 0xf) * 32)
 #define ENETC_PRSSK(n)		(0x1410 + (n) * 4) /* n = [0..9] */
 #define ENETC_PSIVLANFMR	0x1700
 #define ENETC_PSIVLANFMR_VS	BIT(0)
diff --git a/drivers/net/ethernet/freescale/enetc/enetc_pf.c b/drivers/net/ethernet/freescale/enetc/enetc_pf.c
index ed8fcb8b486e..3eb5f1375bd4 100644
--- a/drivers/net/ethernet/freescale/enetc/enetc_pf.c
+++ b/drivers/net/ethernet/freescale/enetc/enetc_pf.c
@@ -996,6 +996,51 @@  static void enetc_phylink_destroy(struct enetc_ndev_priv *priv)
 		phylink_destroy(priv->phylink);
 }
 
+/* Initialize the entire shared memory for the flow steering entries
+ * of this port (PF + VFs)
+ */
+static int enetc_init_port_rfs_memory(struct enetc_si *si)
+{
+	struct enetc_cmd_rfse rfse = {0};
+	struct enetc_hw *hw = &si->hw;
+	int num_rfs, i, err = 0;
+	u32 val;
+
+	val = enetc_port_rd(hw, ENETC_PRFSCAPR);
+	num_rfs = ENETC_PRFSCAPR_GET_NUM_RFS(val);
+
+	for (i = 0; i < num_rfs; i++) {
+		err = enetc_set_fs_entry(si, &rfse, i);
+		if (err)
+			break;
+	}
+
+	return err;
+}
+
+static int enetc_init_port_rss_memory(struct enetc_si *si)
+{
+	struct enetc_hw *hw = &si->hw;
+	int num_rss, err;
+	int *rss_table;
+	u32 val;
+
+	val = enetc_port_rd(hw, ENETC_PRSSCAPR);
+	num_rss = ENETC_PRSSCAPR_GET_NUM_RSS(val);
+	if (!num_rss)
+		return 0;
+
+	rss_table = kcalloc(num_rss, sizeof(*rss_table), GFP_KERNEL);
+	if (!rss_table)
+		return -ENOMEM;
+
+	err = enetc_set_rss_table(si, rss_table, num_rss);
+
+	kfree(rss_table);
+
+	return err;
+}
+
 static int enetc_pf_probe(struct pci_dev *pdev,
 			  const struct pci_device_id *ent)
 {
@@ -1051,6 +1096,18 @@  static int enetc_pf_probe(struct pci_dev *pdev,
 		goto err_alloc_si_res;
 	}
 
+	err = enetc_init_port_rfs_memory(si);
+	if (err) {
+		dev_err(&pdev->dev, "Failed to initialize RFS memory\n");
+		goto err_init_port_rfs;
+	}
+
+	err = enetc_init_port_rss_memory(si);
+	if (err) {
+		dev_err(&pdev->dev, "Failed to initialize RSS memory\n");
+		goto err_init_port_rss;
+	}
+
 	err = enetc_alloc_msix(priv);
 	if (err) {
 		dev_err(&pdev->dev, "MSIX alloc failed\n");
@@ -1079,6 +1136,8 @@  static int enetc_pf_probe(struct pci_dev *pdev,
 	enetc_mdiobus_destroy(pf);
 err_mdiobus_create:
 	enetc_free_msix(priv);
+err_init_port_rss:
+err_init_port_rfs:
 err_alloc_msix:
 	enetc_free_si_resources(priv);
 err_alloc_si_res: