| Message ID | 1612253821-1148-13-git-send-email-stefanc@marvell.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | net: mvpp2: Add TX Flow Control support | expand |
| Context | Check | Description |
|---|---|---|
| netdev/cover_letter | success | Link |
| netdev/fixes_present | success | Link |
| netdev/patch_count | success | Link |
| netdev/tree_selection | success | Clearly marked for net-next |
| netdev/subject_prefix | success | Link |
| netdev/cc_maintainers | success | CCed 5 of 5 maintainers |
| netdev/source_inline | success | Was 0 now: 0 |
| netdev/verify_signedoff | success | Link |
| netdev/module_param | fail | Was 0 now: 1 |
| netdev/build_32bit | success | Errors and warnings before: 5 this patch: 5 |
| netdev/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| netdev/verify_fixes | success | Link |
| netdev/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 85 lines checked |
| netdev/build_allmodconfig_warn | success | Errors and warnings before: 5 this patch: 5 |
| netdev/header_inline | success | Link |
| netdev/stable | success | Stable not CCed |
Hi, wt., 2 lut 2021 o 09:18 <stefanc@marvell.com> napisał(a): > > From: Stefan Chulski <stefanc@marvell.com> > > Feature double size of BPPI by decreasing number of pools from 16 to 8. How about: 'The PP2v23 hardware supports a feature allowing to double the size of...' ? > Increasing of BPPI size protect BM drop from BPPI underrun. > Underrun could occurred due to stress on DDR and as result slow buffer > transition from BPPE to BPPI. > New BPPI threshold recommended by spec is: > BPPI low threshold - 640 buffers > BPPI high threshold - 832 buffers > Supported only in PPv23. > > Signed-off-by: Stefan Chulski <stefanc@marvell.com> > --- > drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 8 +++++ > drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 35 +++++++++++++++++++- > 2 files changed, 42 insertions(+), 1 deletion(-) > > diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h > index 9071ab6..1967493 100644 > --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h > +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h > @@ -324,6 +324,10 @@ > #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000 > #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \ > MVPP2_BM_HIGH_THRESH_OFFS) > +#define MVPP2_BM_BPPI_HIGH_THRESH 0x1E > +#define MVPP2_BM_BPPI_LOW_THRESH 0x1C > +#define MVPP23_BM_BPPI_HIGH_THRESH 0x34 > +#define MVPP23_BM_BPPI_LOW_THRESH 0x28 > #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4)) > #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0) > #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1) > @@ -352,6 +356,10 @@ > #define MVPP2_OVERRUN_ETH_DROP 0x7000 > #define MVPP2_CLS_ETH_DROP 0x7020 > > +#define MVPP22_BM_POOL_BASE_ADDR_HIGH_REG 0x6310 > +#define MVPP22_BM_POOL_BASE_ADDR_HIGH_MASK 0xff > +#define MVPP23_BM_8POOL_MODE BIT(8) > + > /* Hit counters registers */ > #define MVPP2_CTRS_IDX 0x7040 > #define MVPP22_CTRS_TX_CTR(port, txq) ((txq) | ((port) << 3) | BIT(7)) > diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c > index bbefc7e..f153060 100644 > --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c > +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c > @@ -70,6 +70,11 @@ enum mvpp2_bm_pool_log_num { > module_param(queue_mode, int, 0444); > MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)"); > > +static int bm_underrun_protect = 1; > + > +module_param(bm_underrun_protect, int, 0444); > +MODULE_PARM_DESC(bm_underrun_protect, "Set BM underrun protect feature (0-1), def=1"); > + > /* Utility/helper methods */ > > void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) > @@ -424,6 +429,21 @@ static int mvpp2_bm_pool_create(struct device *dev, struct mvpp2 *priv, > > val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); > val |= MVPP2_BM_START_MASK; > + > + val &= ~MVPP2_BM_LOW_THRESH_MASK; > + val &= ~MVPP2_BM_HIGH_THRESH_MASK; > + > + /* Set 8 Pools BPPI threshold if BM underrun protection feature > + * were enabled Nit: s/were/was/ Thanks, Marcin > + */ > + if (priv->hw_version == MVPP23 && bm_underrun_protect) { > + val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP23_BM_BPPI_LOW_THRESH); > + val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP23_BM_BPPI_HIGH_THRESH); > + } else { > + val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP2_BM_BPPI_LOW_THRESH); > + val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP2_BM_BPPI_HIGH_THRESH); > + } > + > mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); > > bm_pool->size = size; > @@ -592,6 +612,16 @@ static int mvpp2_bm_pools_init(struct device *dev, struct mvpp2 *priv) > return err; > } > > +/* Routine enable PPv23 8 pool mode */ > +static void mvpp23_bm_set_8pool_mode(struct mvpp2 *priv) > +{ > + int val; > + > + val = mvpp2_read(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG); > + val |= MVPP23_BM_8POOL_MODE; > + mvpp2_write(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG, val); > +} > + > static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv) > { > enum dma_data_direction dma_dir = DMA_FROM_DEVICE; > @@ -645,6 +675,9 @@ static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv) > if (!priv->bm_pools) > return -ENOMEM; > > + if (priv->hw_version == MVPP23 && bm_underrun_protect) > + mvpp23_bm_set_8pool_mode(priv); > + > err = mvpp2_bm_pools_init(dev, priv); > if (err < 0) > return err; > @@ -6491,7 +6524,7 @@ static void mvpp2_mac_link_up(struct phylink_config *config, > val); > } > > - if (port->priv->global_tx_fc) { > + if (port->priv->global_tx_fc && bm_underrun_protect) { > port->tx_fc = tx_pause; > if (tx_pause) > mvpp2_rxq_enable_fc(port); > -- > 1.9.1 >
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h index 9071ab6..1967493 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h @@ -324,6 +324,10 @@ #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \ MVPP2_BM_HIGH_THRESH_OFFS) +#define MVPP2_BM_BPPI_HIGH_THRESH 0x1E +#define MVPP2_BM_BPPI_LOW_THRESH 0x1C +#define MVPP23_BM_BPPI_HIGH_THRESH 0x34 +#define MVPP23_BM_BPPI_LOW_THRESH 0x28 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4)) #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0) #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1) @@ -352,6 +356,10 @@ #define MVPP2_OVERRUN_ETH_DROP 0x7000 #define MVPP2_CLS_ETH_DROP 0x7020 +#define MVPP22_BM_POOL_BASE_ADDR_HIGH_REG 0x6310 +#define MVPP22_BM_POOL_BASE_ADDR_HIGH_MASK 0xff +#define MVPP23_BM_8POOL_MODE BIT(8) + /* Hit counters registers */ #define MVPP2_CTRS_IDX 0x7040 #define MVPP22_CTRS_TX_CTR(port, txq) ((txq) | ((port) << 3) | BIT(7)) diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c index bbefc7e..f153060 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c @@ -70,6 +70,11 @@ enum mvpp2_bm_pool_log_num { module_param(queue_mode, int, 0444); MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)"); +static int bm_underrun_protect = 1; + +module_param(bm_underrun_protect, int, 0444); +MODULE_PARM_DESC(bm_underrun_protect, "Set BM underrun protect feature (0-1), def=1"); + /* Utility/helper methods */ void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) @@ -424,6 +429,21 @@ static int mvpp2_bm_pool_create(struct device *dev, struct mvpp2 *priv, val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); val |= MVPP2_BM_START_MASK; + + val &= ~MVPP2_BM_LOW_THRESH_MASK; + val &= ~MVPP2_BM_HIGH_THRESH_MASK; + + /* Set 8 Pools BPPI threshold if BM underrun protection feature + * were enabled + */ + if (priv->hw_version == MVPP23 && bm_underrun_protect) { + val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP23_BM_BPPI_LOW_THRESH); + val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP23_BM_BPPI_HIGH_THRESH); + } else { + val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP2_BM_BPPI_LOW_THRESH); + val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP2_BM_BPPI_HIGH_THRESH); + } + mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); bm_pool->size = size; @@ -592,6 +612,16 @@ static int mvpp2_bm_pools_init(struct device *dev, struct mvpp2 *priv) return err; } +/* Routine enable PPv23 8 pool mode */ +static void mvpp23_bm_set_8pool_mode(struct mvpp2 *priv) +{ + int val; + + val = mvpp2_read(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG); + val |= MVPP23_BM_8POOL_MODE; + mvpp2_write(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG, val); +} + static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv) { enum dma_data_direction dma_dir = DMA_FROM_DEVICE; @@ -645,6 +675,9 @@ static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv) if (!priv->bm_pools) return -ENOMEM; + if (priv->hw_version == MVPP23 && bm_underrun_protect) + mvpp23_bm_set_8pool_mode(priv); + err = mvpp2_bm_pools_init(dev, priv); if (err < 0) return err; @@ -6491,7 +6524,7 @@ static void mvpp2_mac_link_up(struct phylink_config *config, val); } - if (port->priv->global_tx_fc) { + if (port->priv->global_tx_fc && bm_underrun_protect) { port->tx_fc = tx_pause; if (tx_pause) mvpp2_rxq_enable_fc(port);