diff mbox series

[v7,net-next,08/15] net: mvpp2: add FCA RXQ non occupied descriptor threshold

Message ID 1612253821-1148-9-git-send-email-stefanc@marvell.com (mailing list archive)
State Superseded
Delegated to: Netdev Maintainers
Headers show
Series net: mvpp2: Add TX Flow Control support | expand

Checks

Context Check Description
netdev/cover_letter success Link
netdev/fixes_present success Link
netdev/patch_count success Link
netdev/tree_selection success Clearly marked for net-next
netdev/subject_prefix success Link
netdev/cc_maintainers success CCed 5 of 5 maintainers
netdev/source_inline success Was 0 now: 0
netdev/verify_signedoff success Link
netdev/module_param success Was 0 now: 0
netdev/build_32bit success Errors and warnings before: 5 this patch: 5
netdev/kdoc success Errors and warnings before: 0 this patch: 0
netdev/verify_fixes success Link
netdev/checkpatch success total: 0 errors, 0 warnings, 0 checks, 104 lines checked
netdev/build_allmodconfig_warn success Errors and warnings before: 5 this patch: 5
netdev/header_inline success Link
netdev/stable success Stable not CCed

Commit Message

Stefan Chulski Feb. 2, 2021, 8:16 a.m. UTC 
From: Stefan Chulski <stefanc@marvell.com>

The firmware needs to monitor the RX Non-occupied descriptor
bits for flow control to move to XOFF mode.
These bits need to be unmasked to be functional, but they will
not raise interrupts as we leave the RX exception summary
bit in MVPP2_ISR_RX_TX_MASK_REG clear.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
---
 drivers/net/ethernet/marvell/mvpp2/mvpp2.h      |  3 ++
 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 44 ++++++++++++++++----
 2 files changed, 40 insertions(+), 7 deletions(-)

Comments

Marcin Wojtas Feb. 4, 2021, 7 p.m. UTC | #1 
Hi,

wt., 2 lut 2021 o 09:18 <stefanc@marvell.com> napisał(a):
>
> From: Stefan Chulski <stefanc@marvell.com>
>
> The firmware needs to monitor the RX Non-occupied descriptor
> bits for flow control to move to XOFF mode.
> These bits need to be unmasked to be functional, but they will
> not raise interrupts as we leave the RX exception summary
> bit in MVPP2_ISR_RX_TX_MASK_REG clear.
>
> Signed-off-by: Stefan Chulski <stefanc@marvell.com>
> ---
>  drivers/net/ethernet/marvell/mvpp2/mvpp2.h      |  3 ++
>  drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 44 ++++++++++++++++----
>  2 files changed, 40 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
> index 73f087c..ca84995 100644
> --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
> +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
> @@ -295,6 +295,8 @@
>  #define     MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK    0x3fc00000
>  #define     MVPP2_PON_CAUSE_MISC_SUM_MASK              BIT(31)
>  #define MVPP2_ISR_MISC_CAUSE_REG               0x55b0
> +#define MVPP2_ISR_RX_ERR_CAUSE_REG(port)       (0x5520 + 4 * (port))
> +#define     MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK 0x00ff
>
>  /* Buffer Manager registers */
>  #define MVPP2_BM_POOL_BASE_REG(pool)           (0x6000 + ((pool) * 4))
> @@ -764,6 +766,7 @@
>  #define MSS_SRAM_SIZE          0x800
>  #define FC_QUANTA              0xFFFF
>  #define FC_CLK_DIVIDER         100
> +#define MSS_THRESHOLD_STOP     768
>
>  /* RX buffer constants */
>  #define MVPP2_SKB_SHINFO_SIZE \
> diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
> index 6e59d07..19a3f38 100644
> --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
> +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
> @@ -1134,14 +1134,19 @@ static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec)
>  static void mvpp2_interrupts_mask(void *arg)
>  {
>         struct mvpp2_port *port = arg;
> +       int cpu = smp_processor_id();
> +       u32 thread;
>
>         /* If the thread isn't used, don't do anything */
> -       if (smp_processor_id() > port->priv->nthreads)
> +       if (cpu >= port->priv->nthreads)

The condition is changed - correctly, but it is a separate fix, that
IMO should go through 'net' tree.

>                 return;
>
> -       mvpp2_thread_write(port->priv,
> -                          mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
> +       thread = mvpp2_cpu_to_thread(port->priv, cpu);
> +
> +       mvpp2_thread_write(port->priv, thread,
>                            MVPP2_ISR_RX_TX_MASK_REG(port->id), 0);
> +       mvpp2_thread_write(port->priv, thread,
> +                          MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), 0);
>  }
>
>  /* Unmask the current thread's Rx/Tx interrupts.
> @@ -1151,20 +1156,25 @@ static void mvpp2_interrupts_mask(void *arg)
>  static void mvpp2_interrupts_unmask(void *arg)
>  {
>         struct mvpp2_port *port = arg;
> -       u32 val;
> +       int cpu = smp_processor_id();
> +       u32 val, thread;
>
>         /* If the thread isn't used, don't do anything */
> -       if (smp_processor_id() > port->priv->nthreads)
> +       if (cpu >= port->priv->nthreads)

Ditto.

Thanks,
Marcin


>                 return;
>
> +       thread = mvpp2_cpu_to_thread(port->priv, cpu);
> +
>         val = MVPP2_CAUSE_MISC_SUM_MASK |
>                 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
>         if (port->has_tx_irqs)
>                 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
>
> -       mvpp2_thread_write(port->priv,
> -                          mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
> +       mvpp2_thread_write(port->priv, thread,
>                            MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
> +       mvpp2_thread_write(port->priv, thread,
> +                          MVPP2_ISR_RX_ERR_CAUSE_REG(port->id),
> +                          MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK);
>  }
>
>  static void
> @@ -1189,6 +1199,9 @@ static void mvpp2_interrupts_unmask(void *arg)
>
>                 mvpp2_thread_write(port->priv, v->sw_thread_id,
>                                    MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
> +               mvpp2_thread_write(port->priv, v->sw_thread_id,
> +                                  MVPP2_ISR_RX_ERR_CAUSE_REG(port->id),
> +                                  MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK);
>         }
>  }
>
> @@ -2394,6 +2407,20 @@ static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
>         }
>  }
>
> +/* Set the number of non-occupied descriptors threshold */
> +static void mvpp2_set_rxq_free_tresh(struct mvpp2_port *port,
> +                                    struct mvpp2_rx_queue *rxq)
> +{
> +       u32 val;
> +
> +       mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
> +
> +       val = mvpp2_read(port->priv, MVPP2_RXQ_THRESH_REG);
> +       val &= ~MVPP2_RXQ_NON_OCCUPIED_MASK;
> +       val |= MSS_THRESHOLD_STOP << MVPP2_RXQ_NON_OCCUPIED_OFFSET;
> +       mvpp2_write(port->priv, MVPP2_RXQ_THRESH_REG, val);
> +}
> +
>  /* Set the number of packets that will be received before Rx interrupt
>   * will be generated by HW.
>   */
> @@ -2649,6 +2676,9 @@ static int mvpp2_rxq_init(struct mvpp2_port *port,
>         mvpp2_rx_pkts_coal_set(port, rxq);
>         mvpp2_rx_time_coal_set(port, rxq);
>
> +       /* Set the number of non occupied descriptors threshold */
> +       mvpp2_set_rxq_free_tresh(port, rxq);
> +
>         /* Add number of descriptors ready for receiving packets */
>         mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
>
> --
> 1.9.1
>
diff mbox series

Patch

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index 73f087c..ca84995 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
@@ -295,6 +295,8 @@ 
 #define     MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK	0x3fc00000
 #define     MVPP2_PON_CAUSE_MISC_SUM_MASK		BIT(31)
 #define MVPP2_ISR_MISC_CAUSE_REG		0x55b0
+#define MVPP2_ISR_RX_ERR_CAUSE_REG(port)	(0x5520 + 4 * (port))
+#define     MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK	0x00ff
 
 /* Buffer Manager registers */
 #define MVPP2_BM_POOL_BASE_REG(pool)		(0x6000 + ((pool) * 4))
@@ -764,6 +766,7 @@ 
 #define MSS_SRAM_SIZE		0x800
 #define FC_QUANTA		0xFFFF
 #define FC_CLK_DIVIDER		100
+#define MSS_THRESHOLD_STOP	768
 
 /* RX buffer constants */
 #define MVPP2_SKB_SHINFO_SIZE \
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index 6e59d07..19a3f38 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -1134,14 +1134,19 @@  static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec)
 static void mvpp2_interrupts_mask(void *arg)
 {
 	struct mvpp2_port *port = arg;
+	int cpu = smp_processor_id();
+	u32 thread;
 
 	/* If the thread isn't used, don't do anything */
-	if (smp_processor_id() > port->priv->nthreads)
+	if (cpu >= port->priv->nthreads)
 		return;
 
-	mvpp2_thread_write(port->priv,
-			   mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
+	thread = mvpp2_cpu_to_thread(port->priv, cpu);
+
+	mvpp2_thread_write(port->priv, thread,
 			   MVPP2_ISR_RX_TX_MASK_REG(port->id), 0);
+	mvpp2_thread_write(port->priv, thread,
+			   MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), 0);
 }
 
 /* Unmask the current thread's Rx/Tx interrupts.
@@ -1151,20 +1156,25 @@  static void mvpp2_interrupts_mask(void *arg)
 static void mvpp2_interrupts_unmask(void *arg)
 {
 	struct mvpp2_port *port = arg;
-	u32 val;
+	int cpu = smp_processor_id();
+	u32 val, thread;
 
 	/* If the thread isn't used, don't do anything */
-	if (smp_processor_id() > port->priv->nthreads)
+	if (cpu >= port->priv->nthreads)
 		return;
 
+	thread = mvpp2_cpu_to_thread(port->priv, cpu);
+
 	val = MVPP2_CAUSE_MISC_SUM_MASK |
 		MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
 	if (port->has_tx_irqs)
 		val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
 
-	mvpp2_thread_write(port->priv,
-			   mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
+	mvpp2_thread_write(port->priv, thread,
 			   MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
+	mvpp2_thread_write(port->priv, thread,
+			   MVPP2_ISR_RX_ERR_CAUSE_REG(port->id),
+			   MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK);
 }
 
 static void
@@ -1189,6 +1199,9 @@  static void mvpp2_interrupts_unmask(void *arg)
 
 		mvpp2_thread_write(port->priv, v->sw_thread_id,
 				   MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
+		mvpp2_thread_write(port->priv, v->sw_thread_id,
+				   MVPP2_ISR_RX_ERR_CAUSE_REG(port->id),
+				   MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK);
 	}
 }
 
@@ -2394,6 +2407,20 @@  static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
 	}
 }
 
+/* Set the number of non-occupied descriptors threshold */
+static void mvpp2_set_rxq_free_tresh(struct mvpp2_port *port,
+				     struct mvpp2_rx_queue *rxq)
+{
+	u32 val;
+
+	mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
+
+	val = mvpp2_read(port->priv, MVPP2_RXQ_THRESH_REG);
+	val &= ~MVPP2_RXQ_NON_OCCUPIED_MASK;
+	val |= MSS_THRESHOLD_STOP << MVPP2_RXQ_NON_OCCUPIED_OFFSET;
+	mvpp2_write(port->priv, MVPP2_RXQ_THRESH_REG, val);
+}
+
 /* Set the number of packets that will be received before Rx interrupt
  * will be generated by HW.
  */
@@ -2649,6 +2676,9 @@  static int mvpp2_rxq_init(struct mvpp2_port *port,
 	mvpp2_rx_pkts_coal_set(port, rxq);
 	mvpp2_rx_time_coal_set(port, rxq);
 
+	/* Set the number of non occupied descriptors threshold */
+	mvpp2_set_rxq_free_tresh(port, rxq);
+
 	/* Add number of descriptors ready for receiving packets */
 	mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);