diff mbox series

clk: qcom: smd: Add missing RPM clocks for msm8992/4

Message ID 20210118161442.104660-1-konrad.dybcio@somainline.org (mailing list archive)
State Not Applicable, archived
Headers show
Series clk: qcom: smd: Add missing RPM clocks for msm8992/4 | expand

Commit Message

Konrad Dybcio Jan. 18, 2021, 4:14 p.m. UTC 
This was omitted when first adding the clocks for these SoCs.

Fixes: b4297844995 ("clk: qcom: smd: Add support for MSM8992/4 rpm clocks")
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
 drivers/clk/qcom/clk-smd-rpm.c         | 16 ++++++++++++++++
 include/dt-bindings/clock/qcom,rpmcc.h |  2 ++
 include/linux/soc/qcom/smd-rpm.h       |  1 +
 3 files changed, 19 insertions(+)

Comments

Stephen Boyd Feb. 8, 2021, 5:50 p.m. UTC | #1 
Quoting Konrad Dybcio (2021-01-18 08:14:41)
> This was omitted when first adding the clocks for these SoCs.
> 

I believe they were omitted because the system crashed if they were
touched. Is that still the case?

> Fixes: b4297844995 ("clk: qcom: smd: Add support for MSM8992/4 rpm clocks")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> ---
>  drivers/clk/qcom/clk-smd-rpm.c         | 16 ++++++++++++++++
>  include/dt-bindings/clock/qcom,rpmcc.h |  2 ++
>  include/linux/soc/qcom/smd-rpm.h       |  1 +
>  3 files changed, 19 insertions(+)
> 
> diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
> index 0e1dfa89489e..91d610042a5d 100644
> --- a/drivers/clk/qcom/clk-smd-rpm.c
> +++ b/drivers/clk/qcom/clk-smd-rpm.c
> @@ -624,6 +624,8 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8976 = {
>  };
>  
>  /* msm8992 */
> +DEFINE_CLK_SMD_RPM_BRANCH(msm8992, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0,
> +                                                               19200000);

This rate should come from some parent clk specified in the board DTS
file as a fixed rate clock.

>  DEFINE_CLK_SMD_RPM(msm8992, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
>  DEFINE_CLK_SMD_RPM(msm8992, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
>  DEFINE_CLK_SMD_RPM(msm8992, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
Konrad Dybcio Feb. 8, 2021, 5:52 p.m. UTC | #2 
On 08.02.2021 18:50, Stephen Boyd wrote:
> Quoting Konrad Dybcio (2021-01-18 08:14:41)
>> This was omitted when first adding the clocks for these SoCs.
>>
> I believe they were omitted because the system crashed if they were
> touched. Is that still the case?

No, rpmcc XO seems to work fine, no crashes around. I just forgot about these the first time around.


>> Fixes: b4297844995 ("clk: qcom: smd: Add support for MSM8992/4 rpm clocks")
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>> ---
>>  drivers/clk/qcom/clk-smd-rpm.c         | 16 ++++++++++++++++
>>  include/dt-bindings/clock/qcom,rpmcc.h |  2 ++
>>  include/linux/soc/qcom/smd-rpm.h       |  1 +
>>  3 files changed, 19 insertions(+)
>>
>> diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
>> index 0e1dfa89489e..91d610042a5d 100644
>> --- a/drivers/clk/qcom/clk-smd-rpm.c
>> +++ b/drivers/clk/qcom/clk-smd-rpm.c
>> @@ -624,6 +624,8 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8976 = {
>>  };
>>  
>>  /* msm8992 */
>> +DEFINE_CLK_SMD_RPM_BRANCH(msm8992, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0,
>> +                                                               19200000);
> This rate should come from some parent clk specified in the board DTS
> file as a fixed rate clock.

The hardcoded-by-design xo_board is 19.2 MHz too, so that matches.


Konrad
diff mbox series

Patch

diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
index 0e1dfa89489e..91d610042a5d 100644
--- a/drivers/clk/qcom/clk-smd-rpm.c
+++ b/drivers/clk/qcom/clk-smd-rpm.c
@@ -624,6 +624,8 @@  static const struct rpm_smd_clk_desc rpm_clk_msm8976 = {
 };
 
 /* msm8992 */
+DEFINE_CLK_SMD_RPM_BRANCH(msm8992, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0,
+								19200000);
 DEFINE_CLK_SMD_RPM(msm8992, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
 DEFINE_CLK_SMD_RPM(msm8992, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
 DEFINE_CLK_SMD_RPM(msm8992, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
@@ -642,6 +644,8 @@  DEFINE_CLK_SMD_RPM(msm8992, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, ln_bb_clk, ln_bb_a_clk, 8);
 DEFINE_CLK_SMD_RPM(msm8992, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk,
 		   QCOM_SMD_RPM_BUS_CLK, 3);
+DEFINE_CLK_SMD_RPM_BRANCH(msm8992, mss_cfg_ahb_clk, mss_cfg_ahb_a_clk,
+			QCOM_SMD_RPM_MFFG_CLK, 0, 19200000);
 DEFINE_CLK_SMD_RPM_QDSS(msm8992, qdss_clk, qdss_a_clk,
 			QCOM_SMD_RPM_MISC_CLK, 1);
 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, rf_clk1, rf_clk1_a, 4);
@@ -653,6 +657,8 @@  DEFINE_CLK_SMD_RPM(msm8992, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
 DEFINE_CLK_SMD_RPM(msm8992, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1);
 
 static struct clk_smd_rpm *msm8992_clks[] = {
+	[RPM_SMD_XO_CLK_SRC] = &msm8992_bi_tcxo,
+	[RPM_SMD_XO_A_CLK_SRC] = &msm8992_bi_tcxo_a,
 	[RPM_SMD_PNOC_CLK] = &msm8992_pnoc_clk,
 	[RPM_SMD_PNOC_A_CLK] = &msm8992_pnoc_a_clk,
 	[RPM_SMD_OCMEMGX_CLK] = &msm8992_ocmemgx_clk,
@@ -685,6 +691,8 @@  static struct clk_smd_rpm *msm8992_clks[] = {
 	[RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
 	[RPM_SMD_MMSSNOC_AHB_CLK] = &msm8992_mmssnoc_ahb_clk,
 	[RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8992_mmssnoc_ahb_a_clk,
+	[RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_mss_cfg_ahb_clk,
+	[RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_mss_cfg_ahb_a_clk,
 	[RPM_SMD_QDSS_CLK] = &msm8992_qdss_clk,
 	[RPM_SMD_QDSS_A_CLK] = &msm8992_qdss_a_clk,
 	[RPM_SMD_RF_CLK1] = &msm8992_rf_clk1,
@@ -707,6 +715,8 @@  static const struct rpm_smd_clk_desc rpm_clk_msm8992 = {
 };
 
 /* msm8994 */
+DEFINE_CLK_SMD_RPM_BRANCH(msm8994, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0,
+								19200000);
 DEFINE_CLK_SMD_RPM(msm8994, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
 DEFINE_CLK_SMD_RPM(msm8994, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
 DEFINE_CLK_SMD_RPM(msm8994, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
@@ -725,6 +735,8 @@  DEFINE_CLK_SMD_RPM(msm8994, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, ln_bb_clk, ln_bb_a_clk, 8);
 DEFINE_CLK_SMD_RPM(msm8994, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk,
 		   QCOM_SMD_RPM_BUS_CLK, 3);
+DEFINE_CLK_SMD_RPM_BRANCH(msm8994, mss_cfg_ahb_clk, mss_cfg_ahb_a_clk,
+			QCOM_SMD_RPM_MFFG_CLK, 0, 19200000);
 DEFINE_CLK_SMD_RPM_QDSS(msm8994, qdss_clk, qdss_a_clk,
 			QCOM_SMD_RPM_MISC_CLK, 1);
 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, rf_clk1, rf_clk1_a, 4);
@@ -737,6 +749,8 @@  DEFINE_CLK_SMD_RPM(msm8994, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1);
 DEFINE_CLK_SMD_RPM(msm8994, ce3_clk, ce3_a_clk, QCOM_SMD_RPM_CE_CLK, 2);
 
 static struct clk_smd_rpm *msm8994_clks[] = {
+	[RPM_SMD_XO_CLK_SRC] = &msm8994_bi_tcxo,
+	[RPM_SMD_XO_A_CLK_SRC] = &msm8994_bi_tcxo_a,
 	[RPM_SMD_PNOC_CLK] = &msm8994_pnoc_clk,
 	[RPM_SMD_PNOC_A_CLK] = &msm8994_pnoc_a_clk,
 	[RPM_SMD_OCMEMGX_CLK] = &msm8994_ocmemgx_clk,
@@ -769,6 +783,8 @@  static struct clk_smd_rpm *msm8994_clks[] = {
 	[RPM_SMD_LN_BB_A_CLK] = &msm8994_ln_bb_a_clk,
 	[RPM_SMD_MMSSNOC_AHB_CLK] = &msm8994_mmssnoc_ahb_clk,
 	[RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8994_mmssnoc_ahb_a_clk,
+	[RPM_SMD_MSS_CFG_AHB_CLK] = &msm8994_mss_cfg_ahb_clk,
+	[RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8994_mss_cfg_ahb_a_clk,
 	[RPM_SMD_QDSS_CLK] = &msm8994_qdss_clk,
 	[RPM_SMD_QDSS_A_CLK] = &msm8994_qdss_a_clk,
 	[RPM_SMD_RF_CLK1] = &msm8994_rf_clk1,
diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h
index 8aaba7cd9589..e8e256dbcc8a 100644
--- a/include/dt-bindings/clock/qcom,rpmcc.h
+++ b/include/dt-bindings/clock/qcom,rpmcc.h
@@ -149,5 +149,7 @@ 
 #define RPM_SMD_CE2_A_CLK			103
 #define RPM_SMD_CE3_CLK				104
 #define RPM_SMD_CE3_A_CLK			105
+#define RPM_SMD_MSS_CFG_AHB_CLK			106
+#define RPM_SMD_MSS_CFG_AHB_A_CLK		107
 
 #endif
diff --git a/include/linux/soc/qcom/smd-rpm.h b/include/linux/soc/qcom/smd-rpm.h
index f2645ec52520..ce51b18f7128 100644
--- a/include/linux/soc/qcom/smd-rpm.h
+++ b/include/linux/soc/qcom/smd-rpm.h
@@ -37,6 +37,7 @@  struct qcom_smd_rpm;
 #define QCOM_SMD_RPM_IPA_CLK	0x617069
 #define QCOM_SMD_RPM_CE_CLK	0x6563
 #define QCOM_SMD_RPM_AGGR_CLK	0x72676761
+#define QCOM_SMD_RPM_MFFG_CLK	0x6766636d
 
 int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,
 		       int state,