Message ID | 20210212140643.23436-1-bjarni.jonasson@microchip.com (mailing list archive) |
---|---|
State | Superseded |
Delegated to: | Netdev Maintainers |
Headers | show |
Series | [net,v1,1/3] net: phy: mscc: adding LCPLL reset to VSC8514 | expand |
Context | Check | Description |
---|---|---|
netdev/cover_letter | warning | Series does not have a cover letter |
netdev/fixes_present | success | Link |
netdev/patch_count | success | Link |
netdev/tree_selection | success | Clearly marked for net |
netdev/subject_prefix | success | Link |
netdev/cc_maintainers | warning | 4 maintainers not CCed: dmurphy@ti.com kavyasree.kotagiri@microchip.com quentin.schulz@bootlin.com michael@walle.cc |
netdev/source_inline | success | Was 0 now: 0 |
netdev/verify_signedoff | success | Link |
netdev/module_param | success | Was 0 now: 0 |
netdev/build_32bit | fail | Errors and warnings before: 0 this patch: 84 |
netdev/kdoc | success | Errors and warnings before: 0 this patch: 0 |
netdev/verify_fixes | success | Link |
netdev/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 326 lines checked |
netdev/build_allmodconfig_warn | fail | Errors and warnings before: 0 this patch: 84 |
netdev/header_inline | success | Link |
netdev/stable | success | Stable not CCed |
On Fri, Feb 12, 2021 at 03:06:41PM +0100, Bjarni Jonasson wrote: > +static u32 vsc85xx_csr_read(struct phy_device *phydev, > + enum csr_target target, u32 reg); > +static int vsc85xx_csr_write(struct phy_device *phydev, > + enum csr_target target, u32 reg, u32 val); > + Hi Bjarni No forward definitions please. Move the code around so they are not required. Sometimes it is best to do such a move as a preparation patch. > @@ -1569,8 +1664,16 @@ static int vsc8514_config_pre_init(struct phy_device *phydev) > {0x16b2, 0x00007000}, > {0x16b4, 0x00000814}, > }; > + struct device *dev = &phydev->mdio.dev; > unsigned int i; > u16 reg; > + int ret; Hard to say from the limited context, but is reverse christmass tree being preserved here? Andrew
On Fri, Feb 12, 2021 at 03:06:41PM +0100, Bjarni Jonasson wrote: > At Power-On Reset, transients may cause the LCPLL to lock onto a > clock that is momentarily unstable. This is normally seen in QSGMII > setups where the higher speed 6G SerDes is being used. > This patch adds an initial LCPLL Reset to the PHY (first instance) > to avoid this issue. Hi Bjarni https://www.kernel.org/doc/html/latest/process/stable-kernel-rules.html These patches are rather large for stable, and not obviously correct. There these problems hitting real users running stable kernels? Or is it so broken it never really worked? Andrew
On Fri, Feb 12, 2021 at 03:06:41PM +0100, Bjarni Jonasson wrote: > At Power-On Reset, transients may cause the LCPLL to lock onto a > clock that is momentarily unstable. This is normally seen in QSGMII > setups where the higher speed 6G SerDes is being used. > This patch adds an initial LCPLL Reset to the PHY (first instance) > to avoid this issue. > > Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> > Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> > Fixes: e4f9ba642f0b ("net: phy: mscc: add support for VSC8514 PHY.") > --- Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> # for regressions
On Fri, 12 Feb 2021 15:06:41 +0100 Bjarni Jonasson wrote: > At Power-On Reset, transients may cause the LCPLL to lock onto a > clock that is momentarily unstable. This is normally seen in QSGMII > setups where the higher speed 6G SerDes is being used. > This patch adds an initial LCPLL Reset to the PHY (first instance) > to avoid this issue. > > Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> > Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> > Fixes: e4f9ba642f0b ("net: phy: mscc: add support for VSC8514 PHY.") Please make sure each commit builds cleanly with W=1 C=1. This one appears to not build at all?
Hi Bjarni, Thank you for the patch! Yet something to improve: [auto build test ERROR on net/master] url: https://github.com/0day-ci/linux/commits/Bjarni-Jonasson/net-phy-mscc-adding-LCPLL-reset-to-VSC8514/20210212-221024 base: https://git.kernel.org/pub/scm/linux/kernel/git/davem/net.git 308daa19e2d0321ff8b037ea192c48358f9324f5 config: x86_64-randconfig-a014-20210209 (attached as .config) compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project c9439ca36342fb6013187d0a69aef92736951476) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install x86_64 cross compiling tool for clang build # apt-get install binutils-x86-64-linux-gnu # https://github.com/0day-ci/linux/commit/fd70d86ef38269af43b612e70cc5edbf06b58db1 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Bjarni-Jonasson/net-phy-mscc-adding-LCPLL-reset-to-VSC8514/20210212-221024 git checkout fd70d86ef38269af43b612e70cc5edbf06b58db1 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@intel.com> All errors (new ones prefixed by >>): In file included from drivers/net/phy/mscc/mscc_main.c:21: >> drivers/net/phy/mscc/mscc.h:420:2: error: redefinition of enumerator 'FC_BUFFER' FC_BUFFER = 0x04, ^ drivers/net/phy/mscc/mscc_macsec.h:64:2: note: previous definition is here FC_BUFFER = 0x04, ^ In file included from drivers/net/phy/mscc/mscc_main.c:21: >> drivers/net/phy/mscc/mscc.h:421:2: error: redefinition of enumerator 'HOST_MAC' HOST_MAC = 0x05, ^ drivers/net/phy/mscc/mscc_macsec.h:65:2: note: previous definition is here HOST_MAC = 0x05, ^ In file included from drivers/net/phy/mscc/mscc_main.c:21: >> drivers/net/phy/mscc/mscc.h:422:2: error: redefinition of enumerator 'LINE_MAC' LINE_MAC = 0x06, ^ drivers/net/phy/mscc/mscc_macsec.h:66:2: note: previous definition is here LINE_MAC = 0x06, ^ In file included from drivers/net/phy/mscc/mscc_main.c:21: >> drivers/net/phy/mscc/mscc.h:430:2: error: redefinition of enumerator 'PROC_0' PROC_0 = 0x0E, ^ drivers/net/phy/mscc/mscc_macsec.h:67:2: note: previous definition is here PROC_0 = 0x0e, ^ In file included from drivers/net/phy/mscc/mscc_main.c:21: >> drivers/net/phy/mscc/mscc.h:431:2: error: redefinition of enumerator 'PROC_2' PROC_2 = 0x0F, ^ drivers/net/phy/mscc/mscc_macsec.h:68:2: note: previous definition is here PROC_2 = 0x0f, ^ In file included from drivers/net/phy/mscc/mscc_main.c:21: >> drivers/net/phy/mscc/mscc.h:432:2: error: redefinition of enumerator 'MACSEC_INGR' MACSEC_INGR = 0x38, ^ drivers/net/phy/mscc/mscc_macsec.h:69:2: note: previous definition is here MACSEC_INGR = 0x38, ^ In file included from drivers/net/phy/mscc/mscc_main.c:21: >> drivers/net/phy/mscc/mscc.h:433:2: error: redefinition of enumerator 'MACSEC_EGR' MACSEC_EGR = 0x3C, ^ drivers/net/phy/mscc/mscc_macsec.h:70:2: note: previous definition is here MACSEC_EGR = 0x3c, ^ 7 errors generated. vim +/FC_BUFFER +420 drivers/net/phy/mscc/mscc.h 418 419 enum csr_target { > 420 FC_BUFFER = 0x04, > 421 HOST_MAC = 0x05, > 422 LINE_MAC = 0x06, 423 MACRO_CTRL = 0x07, 424 ANA0_INGR = 0x08, 425 ANA0_EGR = 0x09, 426 ANA1_INGR = 0x0A, 427 ANA1_EGR = 0x0B, 428 ANA2_INGR = 0x0C, 429 ANA2_EGR = 0x0D, > 430 PROC_0 = 0x0E, > 431 PROC_2 = 0x0F, > 432 MACSEC_INGR = 0x38, > 433 MACSEC_EGR = 0x3C, 434 SPI_IO = 0x40, 435 }; 436 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
On Fri, 2021-02-12 at 16:20 +0100, Andrew Lunn wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you > know the content is safe > > On Fri, Feb 12, 2021 at 03:06:41PM +0100, Bjarni Jonasson wrote: > > +static u32 vsc85xx_csr_read(struct phy_device *phydev, > > + enum csr_target target, u32 reg); > > +static int vsc85xx_csr_write(struct phy_device *phydev, > > + enum csr_target target, u32 reg, u32 > > val); > > + > > Hi Bjarni > > No forward definitions please. Move the code around so they are not > required. Sometimes it is best to do such a move as a preparation > patch. Sure, I will remove them. > > > @@ -1569,8 +1664,16 @@ static int vsc8514_config_pre_init(struct > > phy_device *phydev) > > {0x16b2, 0x00007000}, > > {0x16b4, 0x00000814}, > > }; > > + struct device *dev = &phydev->mdio.dev; > > unsigned int i; > > u16 reg; > > + int ret; > > Hard to say from the limited context, but is reverse christmass tree > being preserved here? I will dobbelcheck. > > Andrew
On Fri, 2021-02-12 at 16:54 +0100, Andrew Lunn wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you > know the content is safe > > On Fri, Feb 12, 2021 at 03:06:41PM +0100, Bjarni Jonasson wrote: > > At Power-On Reset, transients may cause the LCPLL to lock onto a > > clock that is momentarily unstable. This is normally seen in QSGMII > > setups where the higher speed 6G SerDes is being used. > > This patch adds an initial LCPLL Reset to the PHY (first instance) > > to avoid this issue. > > Hi Bjarni > > https://www.kernel.org/doc/html/latest/process/stable-kernel-rules.html > > These patches are rather large for stable, and not obviously correct. > > There these problems hitting real users running stable kernels? Or is > it so broken it never really worked? > > Andrew Correct, the current linux driver is unstable and has never really worked properly. Our in-house SDK driver already have these fixes and the upstreamed version has been lagging behind. And yes the patches are big, we had to pull out the calibration from the 8051 into the driver.
On Fri, 2021-02-12 at 10:53 -0800, Jakub Kicinski wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you > know the content is safe > > On Fri, 12 Feb 2021 15:06:41 +0100 Bjarni Jonasson wrote: > > At Power-On Reset, transients may cause the LCPLL to lock onto a > > clock that is momentarily unstable. This is normally seen in QSGMII > > setups where the higher speed 6G SerDes is being used. > > This patch adds an initial LCPLL Reset to the PHY (first instance) > > to avoid this issue. > > > > Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> > > Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> > > Fixes: e4f9ba642f0b ("net: phy: mscc: add support for VSC8514 > > PHY.") > > Please make sure each commit builds cleanly with W=1 C=1. > > This one appears to not build at all? Sorry about that, I will make sure.
diff --git a/drivers/net/phy/mscc/mscc.h b/drivers/net/phy/mscc/mscc.h index 9481bce94c2e..6343fd49171a 100644 --- a/drivers/net/phy/mscc/mscc.h +++ b/drivers/net/phy/mscc/mscc.h @@ -102,6 +102,7 @@ enum rgmii_clock_delay { #define PHY_MCB_S6G_READ BIT(30) #define PHY_S6G_PLL5G_CFG0 0x06 +#define PHY_S6G_PLL5G_CFG2 0x08 #define PHY_S6G_LCPLL_CFG 0x11 #define PHY_S6G_PLL_CFG 0x2b #define PHY_S6G_COMMON_CFG 0x2c @@ -121,6 +122,9 @@ enum rgmii_clock_delay { #define PHY_S6G_PLL_FSM_CTRL_DATA_POS 8 #define PHY_S6G_PLL_FSM_ENA_POS 7 +#define PHY_S6G_CFG2_FSM_DIS 1 +#define PHY_S6G_CFG2_FSM_CLK_BP 23 + #define MSCC_EXT_PAGE_ACCESS 31 #define MSCC_PHY_PAGE_STANDARD 0x0000 /* Standard registers */ #define MSCC_PHY_PAGE_EXTENDED 0x0001 /* Extended registers */ @@ -412,6 +416,24 @@ struct vsc8531_edge_rate_table { }; #endif /* CONFIG_OF_MDIO */ +enum csr_target { + FC_BUFFER = 0x04, + HOST_MAC = 0x05, + LINE_MAC = 0x06, + MACRO_CTRL = 0x07, + ANA0_INGR = 0x08, + ANA0_EGR = 0x09, + ANA1_INGR = 0x0A, + ANA1_EGR = 0x0B, + ANA2_INGR = 0x0C, + ANA2_EGR = 0x0D, + PROC_0 = 0x0E, + PROC_2 = 0x0F, + MACSEC_INGR = 0x38, + MACSEC_EGR = 0x3C, + SPI_IO = 0x40, +}; + #if IS_ENABLED(CONFIG_MACSEC) int vsc8584_macsec_init(struct phy_device *phydev); void vsc8584_handle_macsec_interrupt(struct phy_device *phydev); diff --git a/drivers/net/phy/mscc/mscc_main.c b/drivers/net/phy/mscc/mscc_main.c index 2f2157e3deab..12c4c1de6001 100644 --- a/drivers/net/phy/mscc/mscc_main.c +++ b/drivers/net/phy/mscc/mscc_main.c @@ -107,6 +107,11 @@ static const struct vsc8531_edge_rate_table edge_table[] = { }; #endif +static u32 vsc85xx_csr_read(struct phy_device *phydev, + enum csr_target target, u32 reg); +static int vsc85xx_csr_write(struct phy_device *phydev, + enum csr_target target, u32 reg, u32 val); + static int vsc85xx_phy_read_page(struct phy_device *phydev) { return __phy_read(phydev, MSCC_EXT_PAGE_ACCESS); @@ -1131,6 +1136,96 @@ static int vsc8574_config_pre_init(struct phy_device *phydev) return ret; } +/* Access LCPLL Cfg_2 */ +static void vsc8584_pll5g_cfg2_wr(struct phy_device *phydev, + bool disable_fsm, bool ena_clk_bypass) +{ + u32 rd_dat; + + rd_dat = vsc85xx_csr_read(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2); + rd_dat &= ~(BIT(PHY_S6G_CFG2_FSM_CLK_BP) | BIT(PHY_S6G_CFG2_FSM_DIS)); + rd_dat |= (disable_fsm << PHY_S6G_CFG2_FSM_DIS) | + (ena_clk_bypass << PHY_S6G_CFG2_FSM_CLK_BP); + vsc85xx_csr_write(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2, rd_dat); +} + +/* trigger a read to the spcified MCB */ +static int vsc8584_mcb_rd_trig(struct phy_device *phydev, + u32 mcb_reg_addr, u8 mcb_slave_num) +{ + u32 rd_dat = 0; + + /* read MCB */ + vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr, + (0x40000000 | (1L << mcb_slave_num))); + + return read_poll_timeout(vsc85xx_csr_read, rd_dat, + !(rd_dat & 0x40000000), + 4000, 200000, 0, + phydev, MACRO_CTRL, mcb_reg_addr); +} + +/* trigger a write to the spcified MCB */ +static int vsc8584_mcb_wr_trig(struct phy_device *phydev, + u32 mcb_reg_addr, + u8 mcb_slave_num) +{ + u32 rd_dat = 0; + + /* write back MCB */ + vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr, + (0x80000000 | (1L << mcb_slave_num))); + + return read_poll_timeout(vsc85xx_csr_read, rd_dat, + !(rd_dat & 0x80000000), + 4000, 200000, 0, + phydev, MACRO_CTRL, mcb_reg_addr); +} + +/* Sequence to Reset LCPLL for the VIPER and ELISE PHY */ +static int vsc8584_pll5g_reset(struct phy_device *phydev) +{ + bool dis_fsm; + bool ena_clk_bypass; + int ret = 0; + + ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0); + if (ret < 0) + goto done; + dis_fsm = 1; + ena_clk_bypass = 0; + + /* Reset LCPLL */ + vsc8584_pll5g_cfg2_wr(phydev, dis_fsm, ena_clk_bypass); + + /* write back LCPLL MCB */ + ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0); + if (ret < 0) + goto done; + + /* 10 mSec sleep while LCPLL is hold in reset */ + usleep_range(10000, 20000); + + /* read LCPLL MCB into CSRs */ + ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0); + if (ret < 0) + goto done; + dis_fsm = 0; + ena_clk_bypass = 0; + + /* Release the Reset of LCPLL */ + vsc8584_pll5g_cfg2_wr(phydev, dis_fsm, ena_clk_bypass); + + /* write back LCPLL MCB */ + ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0); + if (ret < 0) + goto done; + + usleep_range(110000, 200000); +done: + return ret; +} + /* bus->mdio_lock should be locked when using this function */ static int vsc8584_config_pre_init(struct phy_device *phydev) { @@ -1569,8 +1664,16 @@ static int vsc8514_config_pre_init(struct phy_device *phydev) {0x16b2, 0x00007000}, {0x16b4, 0x00000814}, }; + struct device *dev = &phydev->mdio.dev; unsigned int i; u16 reg; + int ret; + + ret = vsc8584_pll5g_reset(phydev); + if (ret < 0) { + dev_err(dev, "failed LCPLL reset, ret: %d\n", ret); + return ret; + } phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); @@ -1605,8 +1708,8 @@ static int vsc8514_config_pre_init(struct phy_device *phydev) return 0; } -static u32 vsc85xx_csr_ctrl_phy_read(struct phy_device *phydev, - u32 target, u32 reg) +static u32 vsc85xx_csr_read(struct phy_device *phydev, + enum csr_target target, u32 reg) { unsigned long deadline; u32 val, val_l, val_h; @@ -1624,11 +1727,17 @@ static u32 vsc85xx_csr_ctrl_phy_read(struct phy_device *phydev, phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20, MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2)); + if ((target >> 2 == 0x1) || (target >> 2 == 0x3)) + /* non-MACsec access */ + target &= 0x3; + else + target = 0; + /* Trigger CSR Action - Read into the CSR's */ phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19, MSCC_PHY_CSR_CNTL_19_CMD | MSCC_PHY_CSR_CNTL_19_READ | MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) | - MSCC_PHY_CSR_CNTL_19_TARGET(target & 0x3)); + MSCC_PHY_CSR_CNTL_19_TARGET(target)); /* Wait for register access*/ deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); @@ -1653,8 +1762,8 @@ static u32 vsc85xx_csr_ctrl_phy_read(struct phy_device *phydev, return (val_h << 16) | val_l; } -static int vsc85xx_csr_ctrl_phy_write(struct phy_device *phydev, - u32 target, u32 reg, u32 val) +static int vsc85xx_csr_write(struct phy_device *phydev, + enum csr_target target, u32 reg, u32 val) { unsigned long deadline; @@ -1677,11 +1786,17 @@ static int vsc85xx_csr_ctrl_phy_write(struct phy_device *phydev, /* Write the Most Significant Word (MSW) (18) */ phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16)); + if ((target >> 2 == 0x1) || (target >> 2 == 0x3)) + /* non-MACsec access */ + target &= 0x3; + else + target = 0; + /* Trigger CSR Action - Write into the CSR's */ phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19, MSCC_PHY_CSR_CNTL_19_CMD | MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) | - MSCC_PHY_CSR_CNTL_19_TARGET(target & 0x3)); + MSCC_PHY_CSR_CNTL_19_TARGET(target)); /* Wait for register access */ deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); @@ -1707,15 +1822,15 @@ static int __phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb, u32 val; int ret; - ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, reg, - op | (1 << mcb)); + ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, reg, + op | (1 << mcb)); if (ret) return -EINVAL; deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); do { usleep_range(500, 1000); - val = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET, reg); + val = vsc85xx_csr_read(phydev, PHY_MCB_TARGET, reg); if (val == 0xffffffff) return -EIO; @@ -1796,41 +1911,41 @@ static int vsc8514_config_init(struct phy_device *phydev) /* lcpll mcb */ phy_update_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0); /* pll5gcfg0 */ - ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, - PHY_S6G_PLL5G_CFG0, 0x7036f145); + ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, + PHY_S6G_PLL5G_CFG0, 0x7036f145); if (ret) goto err; phy_commit_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0); /* pllcfg */ - ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, - PHY_S6G_PLL_CFG, - (3 << PHY_S6G_PLL_ENA_OFFS_POS) | - (120 << PHY_S6G_PLL_FSM_CTRL_DATA_POS) - | (0 << PHY_S6G_PLL_FSM_ENA_POS)); + ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, + PHY_S6G_PLL_CFG, + (3 << PHY_S6G_PLL_ENA_OFFS_POS) | + (120 << PHY_S6G_PLL_FSM_CTRL_DATA_POS) + | (0 << PHY_S6G_PLL_FSM_ENA_POS)); if (ret) goto err; /* commoncfg */ - ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, - PHY_S6G_COMMON_CFG, - (0 << PHY_S6G_SYS_RST_POS) | - (0 << PHY_S6G_ENA_LANE_POS) | - (0 << PHY_S6G_ENA_LOOP_POS) | - (0 << PHY_S6G_QRATE_POS) | - (3 << PHY_S6G_IF_MODE_POS)); + ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, + PHY_S6G_COMMON_CFG, + (0 << PHY_S6G_SYS_RST_POS) | + (0 << PHY_S6G_ENA_LANE_POS) | + (0 << PHY_S6G_ENA_LOOP_POS) | + (0 << PHY_S6G_QRATE_POS) | + (3 << PHY_S6G_IF_MODE_POS)); if (ret) goto err; /* misccfg */ - ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, - PHY_S6G_MISC_CFG, 1); + ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, + PHY_S6G_MISC_CFG, 1); if (ret) goto err; /* gpcfg */ - ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, - PHY_S6G_GPC_CFG, 768); + ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, + PHY_S6G_GPC_CFG, 768); if (ret) goto err; @@ -1841,8 +1956,8 @@ static int vsc8514_config_init(struct phy_device *phydev) usleep_range(500, 1000); phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); /* read 6G MCB into CSRs */ - reg = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET, - PHY_S6G_PLL_STATUS); + reg = vsc85xx_csr_read(phydev, PHY_MCB_TARGET, + PHY_S6G_PLL_STATUS); if (reg == 0xffffffff) { phy_unlock_mdio_bus(phydev); return -EIO; @@ -1856,8 +1971,8 @@ static int vsc8514_config_init(struct phy_device *phydev) } /* misccfg */ - ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, - PHY_S6G_MISC_CFG, 0); + ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, + PHY_S6G_MISC_CFG, 0); if (ret) goto err; @@ -1868,8 +1983,8 @@ static int vsc8514_config_init(struct phy_device *phydev) usleep_range(500, 1000); phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); /* read 6G MCB into CSRs */ - reg = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET, - PHY_S6G_IB_STATUS0); + reg = vsc85xx_csr_read(phydev, PHY_MCB_TARGET, + PHY_S6G_IB_STATUS0); if (reg == 0xffffffff) { phy_unlock_mdio_bus(phydev); return -EIO;