Message ID | 20210219201852.3213914-1-jiancai@google.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [v3] ARM: Implement SLS mitigation | expand |
Hi Jian, On Fri, Feb 19, 2021 at 12:18:40PM -0800, 'Jian Cai' via Clang Built Linux wrote: > This patch adds CONFIG_HARDEN_SLS_ALL that can be used to turn on > -mharden-sls=all, which mitigates the straight-line speculation > vulnerability, speculative execution of the instruction following some > unconditional jumps. Notice -mharden-sls= has other options as below, > and this config turns on the strongest option. > > all: enable all mitigations against Straight Line Speculation that are implemented. > none: disable all mitigations against Straight Line Speculation. > retbr: enable the mitigation against Straight Line Speculation for RET and BR instructions. > blr: enable the mitigation against Straight Line Speculation for BLR instructions. > > Links: > https://reviews.llvm.org/D93221 > https://reviews.llvm.org/D81404 > https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability/downloads/straight-line-speculation > https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability/frequently-asked-questions#SLS2 > > Suggested-by: Manoj Gupta <manojgupta@google.com> > Suggested-by: Nick Desaulniers <ndesaulniers@google.com> > Suggested-by: Nathan Chancellor <nathan@kernel.org> > Suggested-by: David Laight <David.Laight@aculab.com> > Suggested-by: Will Deacon <will@kernel.org> > Reviewed-by: Nathan Chancellor <nathan@kernel.org> My review still stands but in the future, if you significantly change how a patch is structured or works, please drop my tag and let me re-add it. One comment below. > Signed-off-by: Jian Cai <jiancai@google.com> > --- > > Changes v2 -> v3: > Modify linker scripts as Nick suggested to address boot failure > (verified with qemu). Added more details in Kconfig.hardening > description. Disable the config by default. > > arch/arm/Makefile | 4 ++++ > arch/arm/include/asm/vmlinux.lds.h | 4 ++++ > arch/arm/kernel/vmlinux.lds.S | 1 + > arch/arm64/Makefile | 4 ++++ > arch/arm64/kernel/vmlinux.lds.S | 5 +++++ > security/Kconfig.hardening | 10 ++++++++++ > 6 files changed, 28 insertions(+) > > diff --git a/arch/arm/Makefile b/arch/arm/Makefile > index 4aaec9599e8a..11d89ef32da9 100644 > --- a/arch/arm/Makefile > +++ b/arch/arm/Makefile > @@ -48,6 +48,10 @@ CHECKFLAGS += -D__ARMEL__ > KBUILD_LDFLAGS += -EL > endif > > +ifeq ($(CONFIG_HARDEN_SLS_ALL), y) > +KBUILD_CFLAGS += -mharden-sls=all > +endif > + > # > # The Scalar Replacement of Aggregates (SRA) optimization pass in GCC 4.9 and > # later may result in code being generated that handles signed short and signed > diff --git a/arch/arm/include/asm/vmlinux.lds.h b/arch/arm/include/asm/vmlinux.lds.h > index 4a91428c324d..c7f9717511ca 100644 > --- a/arch/arm/include/asm/vmlinux.lds.h > +++ b/arch/arm/include/asm/vmlinux.lds.h > @@ -145,3 +145,7 @@ > __edtcm_data = .; \ > } \ > . = __dtcm_start + SIZEOF(.data_dtcm); > + > +#define SLS_TEXT \ > + ALIGN_FUNCTION(); \ > + *(.text.__llvm_slsblr_thunk_*) > diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S > index f7f4620d59c3..e71f2bc97bae 100644 > --- a/arch/arm/kernel/vmlinux.lds.S > +++ b/arch/arm/kernel/vmlinux.lds.S > @@ -63,6 +63,7 @@ SECTIONS > .text : { /* Real text segment */ > _stext = .; /* Text and read-only data */ > ARM_TEXT > + SLS_TEXT > } > > #ifdef CONFIG_DEBUG_ALIGN_RODATA > diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile > index 90309208bb28..ca7299b356a9 100644 > --- a/arch/arm64/Makefile > +++ b/arch/arm64/Makefile > @@ -34,6 +34,10 @@ $(warning LSE atomics not supported by binutils) > endif > endif > > +ifeq ($(CONFIG_HARDEN_SLS_ALL), y) > +KBUILD_CFLAGS += -mharden-sls=all > +endif > + > cc_has_k_constraint := $(call try-run,echo \ > 'int main(void) { \ > asm volatile("and w0, w0, %w0" :: "K" (4294967295)); \ > diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S > index 4c0b0c89ad59..f8912e42ffcd 100644 > --- a/arch/arm64/kernel/vmlinux.lds.S > +++ b/arch/arm64/kernel/vmlinux.lds.S > @@ -93,6 +93,10 @@ jiffies = jiffies_64; > #define TRAMP_TEXT > #endif > > +#define SLS_TEXT \ > + ALIGN_FUNCTION(); \ > + *(.text.__llvm_slsblr_thunk_*) > + > /* > * The size of the PE/COFF section that covers the kernel image, which > * runs from _stext to _edata, must be a round multiple of the PE/COFF > @@ -144,6 +148,7 @@ SECTIONS > HIBERNATE_TEXT > TRAMP_TEXT > *(.fixup) > + SLS_TEXT > *(.gnu.warning) > . = ALIGN(16); > *(.got) /* Global offset table */ > diff --git a/security/Kconfig.hardening b/security/Kconfig.hardening > index 269967c4fc1b..e70f227019e1 100644 > --- a/security/Kconfig.hardening > +++ b/security/Kconfig.hardening > @@ -121,6 +121,16 @@ choice > > endchoice > > +config HARDEN_SLS_ALL > + bool "enable SLS vulnerability hardening" > + default n > + def_bool $(cc-option,-mharden-sls=all) This is a much more convoluted way of writing: depends on $(cc-option,-mharden-sls=all) "default n" is the default and "def_bool" is short for: bool default <expr> which is defeated by the "default n". > + help > + Enables straight-line speculation vulnerability hardening on ARM and ARM64 > + architectures. It inserts speculation barrier sequences (SB or DSB+ISB > + depending on the target architecture) after RET and BR, and replacing > + BLR with BL+BR sequence. > + > config GCC_PLUGIN_STRUCTLEAK_VERBOSE > bool "Report forcefully initialized variables" > depends on GCC_PLUGIN_STRUCTLEAK > -- > 2.30.0.617.g56c4b15f3c-goog >
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 4aaec9599e8a..11d89ef32da9 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -48,6 +48,10 @@ CHECKFLAGS += -D__ARMEL__ KBUILD_LDFLAGS += -EL endif +ifeq ($(CONFIG_HARDEN_SLS_ALL), y) +KBUILD_CFLAGS += -mharden-sls=all +endif + # # The Scalar Replacement of Aggregates (SRA) optimization pass in GCC 4.9 and # later may result in code being generated that handles signed short and signed diff --git a/arch/arm/include/asm/vmlinux.lds.h b/arch/arm/include/asm/vmlinux.lds.h index 4a91428c324d..c7f9717511ca 100644 --- a/arch/arm/include/asm/vmlinux.lds.h +++ b/arch/arm/include/asm/vmlinux.lds.h @@ -145,3 +145,7 @@ __edtcm_data = .; \ } \ . = __dtcm_start + SIZEOF(.data_dtcm); + +#define SLS_TEXT \ + ALIGN_FUNCTION(); \ + *(.text.__llvm_slsblr_thunk_*) diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index f7f4620d59c3..e71f2bc97bae 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S @@ -63,6 +63,7 @@ SECTIONS .text : { /* Real text segment */ _stext = .; /* Text and read-only data */ ARM_TEXT + SLS_TEXT } #ifdef CONFIG_DEBUG_ALIGN_RODATA diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile index 90309208bb28..ca7299b356a9 100644 --- a/arch/arm64/Makefile +++ b/arch/arm64/Makefile @@ -34,6 +34,10 @@ $(warning LSE atomics not supported by binutils) endif endif +ifeq ($(CONFIG_HARDEN_SLS_ALL), y) +KBUILD_CFLAGS += -mharden-sls=all +endif + cc_has_k_constraint := $(call try-run,echo \ 'int main(void) { \ asm volatile("and w0, w0, %w0" :: "K" (4294967295)); \ diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S index 4c0b0c89ad59..f8912e42ffcd 100644 --- a/arch/arm64/kernel/vmlinux.lds.S +++ b/arch/arm64/kernel/vmlinux.lds.S @@ -93,6 +93,10 @@ jiffies = jiffies_64; #define TRAMP_TEXT #endif +#define SLS_TEXT \ + ALIGN_FUNCTION(); \ + *(.text.__llvm_slsblr_thunk_*) + /* * The size of the PE/COFF section that covers the kernel image, which * runs from _stext to _edata, must be a round multiple of the PE/COFF @@ -144,6 +148,7 @@ SECTIONS HIBERNATE_TEXT TRAMP_TEXT *(.fixup) + SLS_TEXT *(.gnu.warning) . = ALIGN(16); *(.got) /* Global offset table */ diff --git a/security/Kconfig.hardening b/security/Kconfig.hardening index 269967c4fc1b..e70f227019e1 100644 --- a/security/Kconfig.hardening +++ b/security/Kconfig.hardening @@ -121,6 +121,16 @@ choice endchoice +config HARDEN_SLS_ALL + bool "enable SLS vulnerability hardening" + default n + def_bool $(cc-option,-mharden-sls=all) + help + Enables straight-line speculation vulnerability hardening on ARM and ARM64 + architectures. It inserts speculation barrier sequences (SB or DSB+ISB + depending on the target architecture) after RET and BR, and replacing + BLR with BL+BR sequence. + config GCC_PLUGIN_STRUCTLEAK_VERBOSE bool "Report forcefully initialized variables" depends on GCC_PLUGIN_STRUCTLEAK