| Message ID | 20210225155909.1853812-4-maxime@cerno.tech (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/vc4: hdmi: Support the 4k @ 60Hz modes | expand |
Hi Maxime On Thu, 25 Feb 2021 at 15:59, Maxime Ripard <maxime@cerno.tech> wrote: > > The BVB clock rate computation doesn't take into account a mode clock of > 594MHz that we're going to need to support 4k60. > > Signed-off-by: Maxime Ripard <maxime@cerno.tech> > --- > drivers/gpu/drm/vc4/vc4_hdmi.c | 11 +++-------- > 1 file changed, 3 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c > index eee9751009c2..b5bc742993a4 100644 > --- a/drivers/gpu/drm/vc4/vc4_hdmi.c > +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c > @@ -91,7 +91,6 @@ > # define VC4_HD_M_ENABLE BIT(0) > > #define CEC_CLOCK_FREQ 40000 > -#define VC4_HSM_MID_CLOCK 149985000 > > #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) > > @@ -739,7 +738,7 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, > conn_state_to_vc4_hdmi_conn_state(conn_state); > struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; > struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); > - unsigned long pixel_rate, hsm_rate; > + unsigned long bvb_rate, pixel_rate, hsm_rate; > int ret; > > ret = pm_runtime_get_sync(&vc4_hdmi->pdev->dev); > @@ -793,12 +792,8 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, > > vc4_hdmi_cec_update_clk_div(vc4_hdmi); > > - /* > - * FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup > - * at 300MHz. > - */ > - ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, > - (hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000)); > + bvb_rate = roundup(mode->clock * 1000 / 2, 75000000); Minor hesitation here that I would need to check the hardware over. As I read your code, if the clock falls 300MHz and 450MHz then you'd ask for a bvb_rate of 225MHz. Depending on what the source clock is that may not be valid. The firmware goes for 75, 150, or 300MHz only. Dave > + ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); > if (ret) { > DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); > clk_disable_unprepare(vc4_hdmi->hsm_clock); > -- > 2.29.2 >
On Thu, 25 Feb 2021 at 16:44, Dave Stevenson <dave.stevenson@raspberrypi.com> wrote: > > Hi Maxime > > On Thu, 25 Feb 2021 at 15:59, Maxime Ripard <maxime@cerno.tech> wrote: > > > > The BVB clock rate computation doesn't take into account a mode clock of > > 594MHz that we're going to need to support 4k60. > > > > Signed-off-by: Maxime Ripard <maxime@cerno.tech> > > --- > > drivers/gpu/drm/vc4/vc4_hdmi.c | 11 +++-------- > > 1 file changed, 3 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c > > index eee9751009c2..b5bc742993a4 100644 > > --- a/drivers/gpu/drm/vc4/vc4_hdmi.c > > +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c > > @@ -91,7 +91,6 @@ > > # define VC4_HD_M_ENABLE BIT(0) > > > > #define CEC_CLOCK_FREQ 40000 > > -#define VC4_HSM_MID_CLOCK 149985000 > > > > #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) > > > > @@ -739,7 +738,7 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, > > conn_state_to_vc4_hdmi_conn_state(conn_state); > > struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; > > struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); > > - unsigned long pixel_rate, hsm_rate; > > + unsigned long bvb_rate, pixel_rate, hsm_rate; > > int ret; > > > > ret = pm_runtime_get_sync(&vc4_hdmi->pdev->dev); > > @@ -793,12 +792,8 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, > > > > vc4_hdmi_cec_update_clk_div(vc4_hdmi); > > > > - /* > > - * FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup > > - * at 300MHz. > > - */ > > - ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, > > - (hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000)); > > + bvb_rate = roundup(mode->clock * 1000 / 2, 75000000); > > Minor hesitation here that I would need to check the hardware over. > As I read your code, if the clock falls 300MHz and 450MHz then you'd > ask for a bvb_rate of 225MHz. Depending on what the source clock is > that may not be valid. > The firmware goes for 75, 150, or 300MHz only. The information I have says it has to be an integer divide of 600MHz (PLLC @ 3GHz / 5), so 225MHz is not valid. (Minor contradictory information though as PLLC is bumped to 3.3GHz with enable_4kp60, but we still appear to get 300MHz for BVB after the /5. A little more checking warranted around here). > Dave > > > + ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); > > if (ret) { > > DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); > > clk_disable_unprepare(vc4_hdmi->hsm_clock); > > -- > > 2.29.2 > >
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c index eee9751009c2..b5bc742993a4 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c @@ -91,7 +91,6 @@ # define VC4_HD_M_ENABLE BIT(0) #define CEC_CLOCK_FREQ 40000 -#define VC4_HSM_MID_CLOCK 149985000 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) @@ -739,7 +738,7 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, conn_state_to_vc4_hdmi_conn_state(conn_state); struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); - unsigned long pixel_rate, hsm_rate; + unsigned long bvb_rate, pixel_rate, hsm_rate; int ret; ret = pm_runtime_get_sync(&vc4_hdmi->pdev->dev); @@ -793,12 +792,8 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, vc4_hdmi_cec_update_clk_div(vc4_hdmi); - /* - * FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup - * at 300MHz. - */ - ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, - (hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000)); + bvb_rate = roundup(mode->clock * 1000 / 2, 75000000); + ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); if (ret) { DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); clk_disable_unprepare(vc4_hdmi->hsm_clock);
The BVB clock rate computation doesn't take into account a mode clock of 594MHz that we're going to need to support 4k60. Signed-off-by: Maxime Ripard <maxime@cerno.tech> --- drivers/gpu/drm/vc4/vc4_hdmi.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-)