| Message ID | 161478622280.16275.6399866734509127420.stgit@bmoger-ubuntu (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] i386: Add missing cpu feature bits in EPYC-Rome model | expand |
On Wednesday, 2021-03-03 at 09:45:30 -06, Babu Moger wrote: > Found the following cpu feature bits missing from EPYC-Rome model. > ibrs : Indirect Branch Restricted Speculation > ssbd : Speculative Store Bypass Disable > > These new features will be added in EPYC-Rome-v2. The -cpu help output > after the change. > > x86 EPYC-Rome (alias configured by machine type) > x86 EPYC-Rome-v1 AMD EPYC-Rome Processor > x86 EPYC-Rome-v2 AMD EPYC-Rome Processor > > Reported-by: Pankaj Gupta <pankaj.gupta@cloud.ionos.com> > Signed-off-by: Babu Moger <babu.moger@amd.com> > Signed-off-by: Pankaj Gupta <pankaj.gupta@cloud.ionos.com> Reviewed-by: David Edmondson <david.edmondson@oracle.com> > --- > v2: Model-id remains same between EPYC-Rome-v1 and EPYC-Rome-v2. > Removed model-id in the patch. > > target/i386/cpu.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 6a53446e6a..30e7188b0e 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -4179,6 +4179,18 @@ static X86CPUDefinition builtin_x86_defs[] = { > .xlevel = 0x8000001E, > .model_id = "AMD EPYC-Rome Processor", > .cache_info = &epyc_rome_cache_info, > + .versions = (X86CPUVersionDefinition[]) { > + { .version = 1 }, > + { > + .version = 2, > + .props = (PropValue[]) { > + { "ibrs", "on" }, > + { "amd-ssbd", "on" }, > + { /* end of list */ } > + } > + }, > + { /* end of list */ } > + } > }, > { > .name = "EPYC-Milan", dme.
> -----Original Message----- > From: Christian Ehrhardt <christian.ehrhardt@canonical.com> > Sent: Thursday, April 1, 2021 3:06 AM > To: david.edmondson@oracle.com > Cc: Moger, Babu <Babu.Moger@amd.com>; Paolo Bonzini > <pbonzini@redhat.com>; Richard Henderson > <richard.henderson@linaro.org>; Eduardo Habkost > <ehabkost@redhat.com>; pankaj.gupta@cloud.ionos.com > Subject: Re: [PATCH v2] i386: Add missing cpu feature bits in EPYC-Rome > model > > On Wed, Mar 3, 2021 at 5:24 PM <david.edmondson@oracle.com> wrote: > > > > On Wednesday, 2021-03-03 at 09:45:30 -06, Babu Moger wrote: > > > > > Found the following cpu feature bits missing from EPYC-Rome model. > > > ibrs : Indirect Branch Restricted Speculation > > > ssbd : Speculative Store Bypass Disable > > > > > > These new features will be added in EPYC-Rome-v2. The -cpu help > > > output after the change. > > > > > > x86 EPYC-Rome (alias configured by machine type) > > > x86 EPYC-Rome-v1 AMD EPYC-Rome Processor > > > x86 EPYC-Rome-v2 AMD EPYC-Rome Processor > > > > > > Reported-by: Pankaj Gupta <pankaj.gupta@cloud.ionos.com> > > > Signed-off-by: Babu Moger <babu.moger@amd.com> > > > Signed-off-by: Pankaj Gupta <pankaj.gupta@cloud.ionos.com> > > > > Reviewed-by: David Edmondson <david.edmondson@oracle.com> > > Hi, > this change/discussion seems as it was good back then but I realized it wasn't > applied in git yet. > Was there a different thread discussing what holds it back that I could not yet > find? > Since we are already in v6.0.0-rc1 the window to get it in shrinks, so I wanted > to give this a gentle ping. Eduardo, Do you have any concerns with these patches? It is also fixing another problem reported here. https://bugs.launchpad.net/ubuntu/+source/qemu/+bug/1915063 Can you please pull these changes? Thanks Babu
On Thu, Apr 08, 2021 at 10:28:21AM -0500, Babu Moger wrote: > > > > -----Original Message----- > > From: Christian Ehrhardt <christian.ehrhardt@canonical.com> > > Sent: Thursday, April 1, 2021 3:06 AM > > To: david.edmondson@oracle.com > > Cc: Moger, Babu <Babu.Moger@amd.com>; Paolo Bonzini > > <pbonzini@redhat.com>; Richard Henderson > > <richard.henderson@linaro.org>; Eduardo Habkost > > <ehabkost@redhat.com>; pankaj.gupta@cloud.ionos.com > > Subject: Re: [PATCH v2] i386: Add missing cpu feature bits in EPYC-Rome > > model > > > > On Wed, Mar 3, 2021 at 5:24 PM <david.edmondson@oracle.com> wrote: > > > > > > On Wednesday, 2021-03-03 at 09:45:30 -06, Babu Moger wrote: > > > > > > > Found the following cpu feature bits missing from EPYC-Rome model. > > > > ibrs : Indirect Branch Restricted Speculation > > > > ssbd : Speculative Store Bypass Disable > > > > > > > > These new features will be added in EPYC-Rome-v2. The -cpu help > > > > output after the change. > > > > > > > > x86 EPYC-Rome (alias configured by machine type) > > > > x86 EPYC-Rome-v1 AMD EPYC-Rome Processor > > > > x86 EPYC-Rome-v2 AMD EPYC-Rome Processor > > > > > > > > Reported-by: Pankaj Gupta <pankaj.gupta@cloud.ionos.com> > > > > Signed-off-by: Babu Moger <babu.moger@amd.com> > > > > Signed-off-by: Pankaj Gupta <pankaj.gupta@cloud.ionos.com> > > > > > > Reviewed-by: David Edmondson <david.edmondson@oracle.com> > > > > Hi, > > this change/discussion seems as it was good back then but I realized it wasn't > > applied in git yet. > > Was there a different thread discussing what holds it back that I could not yet > > find? > > Since we are already in v6.0.0-rc1 the window to get it in shrinks, so I wanted > > to give this a gentle ping. > > Eduardo, > Do you have any concerns with these patches? It is also fixing another > problem reported here. > https://bugs.launchpad.net/ubuntu/+source/qemu/+bug/1915063 > Can you please pull these changes? I'm so sorry for missing this when it was submitted in March. I'm queueing it right now and I'm going to submit a pull request very soon, for -rc4.
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6a53446e6a..30e7188b0e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4179,6 +4179,18 @@ static X86CPUDefinition builtin_x86_defs[] = { .xlevel = 0x8000001E, .model_id = "AMD EPYC-Rome Processor", .cache_info = &epyc_rome_cache_info, + .versions = (X86CPUVersionDefinition[]) { + { .version = 1 }, + { + .version = 2, + .props = (PropValue[]) { + { "ibrs", "on" }, + { "amd-ssbd", "on" }, + { /* end of list */ } + } + }, + { /* end of list */ } + } }, { .name = "EPYC-Milan",