diff mbox series

[1/3] drm/i915/display: Move dc3co_exitline variable to struct intel_psr

Message ID 20210303164201.31301-1-gwan-gyeong.mun@intel.com (mailing list archive)
State New, archived
Headers show
Series [1/3] drm/i915/display: Move dc3co_exitline variable to struct intel_psr | expand

Commit Message

Gwan-gyeong Mun March 3, 2021, 4:41 p.m. UTC 
dc3co_exitline is indirectly called by intel_psr_compute_config().
And it will not be changed until the next calling of
intel_psr_compute_config(). So in order to use dc3co_exitline without
intel_crtc_state on other psr internal function, it moves dc3co_exitline
variable to struct intel_psr.
And it removes a dc3co_enabled variable from struct intel_psr.

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h |  3 +--
 drivers/gpu/drm/i915/display/intel_psr.c           | 11 +++++------
 2 files changed, 6 insertions(+), 8 deletions(-)

Comments

Ville Syrjälä March 3, 2021, 4:54 p.m. UTC | #1 
On Wed, Mar 03, 2021 at 06:41:59PM +0200, Gwan-gyeong Mun wrote:
> dc3co_exitline is indirectly called by intel_psr_compute_config().
> And it will not be changed until the next calling of
> intel_psr_compute_config(). So in order to use dc3co_exitline without
> intel_crtc_state on other psr internal function, it moves dc3co_exitline
> variable to struct intel_psr.
> And it removes a dc3co_enabled variable from struct intel_psr.
> 
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_types.h |  3 +--
>  drivers/gpu/drm/i915/display/intel_psr.c           | 11 +++++------
>  2 files changed, 6 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 1a76e1d9de7a..f69bd1caebbf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1002,7 +1002,6 @@ struct intel_crtc_state {
>  	bool has_psr;
>  	bool has_psr2;
>  	bool enable_psr2_sel_fetch;
> -	u32 dc3co_exitline;
>  
>  	/*
>  	 * Frequence the dpll for the port should run at. Differs from the
> @@ -1453,7 +1452,7 @@ struct intel_psr {
>  	bool sink_not_reliable;
>  	bool irq_aux_error;
>  	u16 su_x_granularity;
> -	bool dc3co_enabled;
> +	u32 dc3co_exitline;
>  	u32 dc3co_exit_delay;
>  	struct delayed_work dc3co_work;
>  	struct drm_dp_vsc_sdp vsc;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index cd434285e3b7..976826653143 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -637,7 +637,7 @@ static void tgl_dc3co_disable_work(struct work_struct *work)
>  
>  static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp)
>  {
> -	if (!intel_dp->psr.dc3co_enabled)
> +	if (!intel_dp->psr.dc3co_exitline)
>  		return;
>  
>  	cancel_delayed_work(&intel_dp->psr.dc3co_work);
> @@ -679,7 +679,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
>  	if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay))
>  		return;
>  
> -	crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines;
> +	intel_dp->psr.dc3co_exitline = crtc_vdisplay - exit_scanlines;

Thou shalt not mutate externally visible state in .compute_config().
You either want to make a copy of it or just compute it on the spot in
the psr_enable(). The first option is a good choice when you can also
hook into into the readout+state checker.

>  }
>  
>  static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> @@ -938,7 +938,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
>  
>  	psr_irq_control(intel_dp);
>  
> -	if (crtc_state->dc3co_exitline) {
> +	if (intel_dp->psr.dc3co_exitline) {
>  		u32 val;
>  
>  		/*
> @@ -947,7 +947,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
>  		 */
>  		val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder));
>  		val &= ~EXITLINE_MASK;
> -		val |= crtc_state->dc3co_exitline << EXITLINE_SHIFT;
> +		val |= intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT;
>  		val |= EXITLINE_ENABLE;
>  		intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val);
>  	}
> @@ -972,7 +972,6 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
>  	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
>  	intel_dp->psr.busy_frontbuffer_bits = 0;
>  	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> -	intel_dp->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
>  	intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
>  	/* DC5/DC6 requires at least 6 idle frames */
>  	val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
> @@ -1761,7 +1760,7 @@ tgl_dc3co_flush(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
>  {
>  	mutex_lock(&intel_dp->psr.lock);
>  
> -	if (!intel_dp->psr.dc3co_enabled)
> +	if (!intel_dp->psr.dc3co_exitline)
>  		goto unlock;
>  
>  	if (!intel_dp->psr.psr2_enabled || !intel_dp->psr.active)
> -- 
> 2.30.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Gwan-gyeong Mun March 5, 2021, 8 p.m. UTC | #2 
On Wed, 2021-03-03 at 18:54 +0200, Ville Syrjälä wrote:
> On Wed, Mar 03, 2021 at 06:41:59PM +0200, Gwan-gyeong Mun wrote:
> > dc3co_exitline is indirectly called by intel_psr_compute_config().
> > And it will not be changed until the next calling of
> > intel_psr_compute_config(). So in order to use dc3co_exitline without
> > intel_crtc_state on other psr internal function, it moves
> > dc3co_exitline
> > variable to struct intel_psr.
> > And it removes a dc3co_enabled variable from struct intel_psr.
> > 
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display_types.h |  3 +--
> >  drivers/gpu/drm/i915/display/intel_psr.c           | 11 +++++------
> >  2 files changed, 6 insertions(+), 8 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 1a76e1d9de7a..f69bd1caebbf 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1002,7 +1002,6 @@ struct intel_crtc_state {
> >         bool has_psr;
> >         bool has_psr2;
> >         bool enable_psr2_sel_fetch;
> > -       u32 dc3co_exitline;
> >  
> >         /*
> >          * Frequence the dpll for the port should run at. Differs
> > from the
> > @@ -1453,7 +1452,7 @@ struct intel_psr {
> >         bool sink_not_reliable;
> >         bool irq_aux_error;
> >         u16 su_x_granularity;
> > -       bool dc3co_enabled;
> > +       u32 dc3co_exitline;
> >         u32 dc3co_exit_delay;
> >         struct delayed_work dc3co_work;
> >         struct drm_dp_vsc_sdp vsc;
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index cd434285e3b7..976826653143 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -637,7 +637,7 @@ static void tgl_dc3co_disable_work(struct
> > work_struct *work)
> >  
> >  static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp
> > *intel_dp)
> >  {
> > -       if (!intel_dp->psr.dc3co_enabled)
> > +       if (!intel_dp->psr.dc3co_exitline)
> >                 return;
> >  
> >         cancel_delayed_work(&intel_dp->psr.dc3co_work);
> > @@ -679,7 +679,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp
> > *intel_dp,
> >         if (drm_WARN_ON(&dev_priv->drm, exit_scanlines >
> > crtc_vdisplay))
> >                 return;
> >  
> > -       crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines;
> > +       intel_dp->psr.dc3co_exitline = crtc_vdisplay -
> > exit_scanlines;
> 
> Thou shalt not mutate externally visible state in .compute_config().
> You either want to make a copy of it or just compute it on the spot in
> the psr_enable(). The first option is a good choice when you can also
> hook into into the readout+state checker.
> 
Hi, thanks for pointing out where I was approached incorrectly.
I'll float new patch that makes copy crtc_state's dc3co_exitline to
intel_psr.dc3co_exitline.

> >  }
> >  
> >  static bool intel_psr2_sel_fetch_config_valid(struct intel_dp
> > *intel_dp,
> > @@ -938,7 +938,7 @@ static void intel_psr_enable_source(struct
> > intel_dp *intel_dp,
> >  
> >         psr_irq_control(intel_dp);
> >  
> > -       if (crtc_state->dc3co_exitline) {
> > +       if (intel_dp->psr.dc3co_exitline) {
> >                 u32 val;
> >  
> >                 /*
> > @@ -947,7 +947,7 @@ static void intel_psr_enable_source(struct
> > intel_dp *intel_dp,
> >                  */
> >                 val = intel_de_read(dev_priv,
> > EXITLINE(cpu_transcoder));
> >                 val &= ~EXITLINE_MASK;
> > -               val |= crtc_state->dc3co_exitline << EXITLINE_SHIFT;
> > +               val |= intel_dp->psr.dc3co_exitline <<
> > EXITLINE_SHIFT;
> >                 val |= EXITLINE_ENABLE;
> >                 intel_de_write(dev_priv, EXITLINE(cpu_transcoder),
> > val);
> >         }
> > @@ -972,7 +972,6 @@ static void intel_psr_enable_locked(struct
> > intel_dp *intel_dp,
> >         intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> >         intel_dp->psr.busy_frontbuffer_bits = 0;
> >         intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)-
> > >pipe;
> > -       intel_dp->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
> >         intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> >         /* DC5/DC6 requires at least 6 idle frames */
> >         val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) *
> > 6);
> > @@ -1761,7 +1760,7 @@ tgl_dc3co_flush(struct intel_dp *intel_dp,
> > unsigned int frontbuffer_bits,
> >  {
> >         mutex_lock(&intel_dp->psr.lock);
> >  
> > -       if (!intel_dp->psr.dc3co_enabled)
> > +       if (!intel_dp->psr.dc3co_exitline)
> >                 goto unlock;
> >  
> >         if (!intel_dp->psr.psr2_enabled || !intel_dp->psr.active)
> > -- 
> > 2.30.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 1a76e1d9de7a..f69bd1caebbf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1002,7 +1002,6 @@  struct intel_crtc_state {
 	bool has_psr;
 	bool has_psr2;
 	bool enable_psr2_sel_fetch;
-	u32 dc3co_exitline;
 
 	/*
 	 * Frequence the dpll for the port should run at. Differs from the
@@ -1453,7 +1452,7 @@  struct intel_psr {
 	bool sink_not_reliable;
 	bool irq_aux_error;
 	u16 su_x_granularity;
-	bool dc3co_enabled;
+	u32 dc3co_exitline;
 	u32 dc3co_exit_delay;
 	struct delayed_work dc3co_work;
 	struct drm_dp_vsc_sdp vsc;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index cd434285e3b7..976826653143 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -637,7 +637,7 @@  static void tgl_dc3co_disable_work(struct work_struct *work)
 
 static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp)
 {
-	if (!intel_dp->psr.dc3co_enabled)
+	if (!intel_dp->psr.dc3co_exitline)
 		return;
 
 	cancel_delayed_work(&intel_dp->psr.dc3co_work);
@@ -679,7 +679,7 @@  tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
 	if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay))
 		return;
 
-	crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines;
+	intel_dp->psr.dc3co_exitline = crtc_vdisplay - exit_scanlines;
 }
 
 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
@@ -938,7 +938,7 @@  static void intel_psr_enable_source(struct intel_dp *intel_dp,
 
 	psr_irq_control(intel_dp);
 
-	if (crtc_state->dc3co_exitline) {
+	if (intel_dp->psr.dc3co_exitline) {
 		u32 val;
 
 		/*
@@ -947,7 +947,7 @@  static void intel_psr_enable_source(struct intel_dp *intel_dp,
 		 */
 		val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder));
 		val &= ~EXITLINE_MASK;
-		val |= crtc_state->dc3co_exitline << EXITLINE_SHIFT;
+		val |= intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT;
 		val |= EXITLINE_ENABLE;
 		intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val);
 	}
@@ -972,7 +972,6 @@  static void intel_psr_enable_locked(struct intel_dp *intel_dp,
 	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
 	intel_dp->psr.busy_frontbuffer_bits = 0;
 	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
-	intel_dp->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
 	intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
 	/* DC5/DC6 requires at least 6 idle frames */
 	val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
@@ -1761,7 +1760,7 @@  tgl_dc3co_flush(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
 {
 	mutex_lock(&intel_dp->psr.lock);
 
-	if (!intel_dp->psr.dc3co_enabled)
+	if (!intel_dp->psr.dc3co_exitline)
 		goto unlock;
 
 	if (!intel_dp->psr.psr2_enabled || !intel_dp->psr.active)