| Message ID | 20210222085756.14396-8-frankja@linux.ibm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | s390x: Cleanup exception register save/restore and implement backtrace | expand |
On 22/02/2021 09.57, Janosch Frank wrote: > There are no more users. At the same time remove sw_int_fpc and > sw_int_frps plus their asm offsets macros since they are also unused > now. > > Signed-off-by: Janosch Frank <frankja@linux.ibm.com> > Reviewed-by: Claudio Imbrenda <imbrenda@linux.ibm.com> > Reviewed-by: Pierre Morel <pmorel@linux.ibm.com> > --- > lib/s390x/asm-offsets.c | 2 -- > lib/s390x/asm/arch_def.h | 4 +--- > s390x/macros.S | 29 ----------------------------- > 3 files changed, 1 insertion(+), 34 deletions(-) > > diff --git a/lib/s390x/asm-offsets.c b/lib/s390x/asm-offsets.c > index 2658b59a..fbea3278 100644 > --- a/lib/s390x/asm-offsets.c > +++ b/lib/s390x/asm-offsets.c > @@ -54,8 +54,6 @@ int main(void) > OFFSET(GEN_LC_MCCK_NEW_PSW, lowcore, mcck_new_psw); > OFFSET(GEN_LC_IO_NEW_PSW, lowcore, io_new_psw); > OFFSET(GEN_LC_SW_INT_GRS, lowcore, sw_int_grs); > - OFFSET(GEN_LC_SW_INT_FPRS, lowcore, sw_int_fprs); > - OFFSET(GEN_LC_SW_INT_FPC, lowcore, sw_int_fpc); > OFFSET(GEN_LC_SW_INT_CRS, lowcore, sw_int_crs); > OFFSET(GEN_LC_SW_INT_PSW, lowcore, sw_int_psw); > OFFSET(GEN_LC_MCCK_EXT_SA_ADDR, lowcore, mcck_ext_sa_addr); > diff --git a/lib/s390x/asm/arch_def.h b/lib/s390x/asm/arch_def.h > index b8e9fe40..13e19b8a 100644 > --- a/lib/s390x/asm/arch_def.h > +++ b/lib/s390x/asm/arch_def.h > @@ -103,9 +103,7 @@ struct lowcore { > struct psw io_new_psw; /* 0x01f0 */ > /* sw definition: save area for registers in interrupt handlers */ > uint64_t sw_int_grs[16]; /* 0x0200 */ > - uint64_t sw_int_fprs[16]; /* 0x0280 */ > - uint32_t sw_int_fpc; /* 0x0300 */ > - uint8_t pad_0x0304[0x0308 - 0x0304]; /* 0x0304 */ > + uint8_t pad_0x0304[0x0308 - 0x0280]; /* 0x0280 */ Please rename to pad_0x280 now. With that fixed: Reviewed-by: Thomas Huth <thuth@redhat.com>
diff --git a/lib/s390x/asm-offsets.c b/lib/s390x/asm-offsets.c index 2658b59a..fbea3278 100644 --- a/lib/s390x/asm-offsets.c +++ b/lib/s390x/asm-offsets.c @@ -54,8 +54,6 @@ int main(void) OFFSET(GEN_LC_MCCK_NEW_PSW, lowcore, mcck_new_psw); OFFSET(GEN_LC_IO_NEW_PSW, lowcore, io_new_psw); OFFSET(GEN_LC_SW_INT_GRS, lowcore, sw_int_grs); - OFFSET(GEN_LC_SW_INT_FPRS, lowcore, sw_int_fprs); - OFFSET(GEN_LC_SW_INT_FPC, lowcore, sw_int_fpc); OFFSET(GEN_LC_SW_INT_CRS, lowcore, sw_int_crs); OFFSET(GEN_LC_SW_INT_PSW, lowcore, sw_int_psw); OFFSET(GEN_LC_MCCK_EXT_SA_ADDR, lowcore, mcck_ext_sa_addr); diff --git a/lib/s390x/asm/arch_def.h b/lib/s390x/asm/arch_def.h index b8e9fe40..13e19b8a 100644 --- a/lib/s390x/asm/arch_def.h +++ b/lib/s390x/asm/arch_def.h @@ -103,9 +103,7 @@ struct lowcore { struct psw io_new_psw; /* 0x01f0 */ /* sw definition: save area for registers in interrupt handlers */ uint64_t sw_int_grs[16]; /* 0x0200 */ - uint64_t sw_int_fprs[16]; /* 0x0280 */ - uint32_t sw_int_fpc; /* 0x0300 */ - uint8_t pad_0x0304[0x0308 - 0x0304]; /* 0x0304 */ + uint8_t pad_0x0304[0x0308 - 0x0280]; /* 0x0280 */ uint64_t sw_int_crs[16]; /* 0x0308 */ struct psw sw_int_psw; /* 0x0388 */ uint8_t pad_0x0310[0x11b0 - 0x0398]; /* 0x0398 */ diff --git a/s390x/macros.S b/s390x/macros.S index d4f41ec4..13cff299 100644 --- a/s390x/macros.S +++ b/s390x/macros.S @@ -33,35 +33,6 @@ lpswe \old_psw .endm - .macro SAVE_REGS - /* save grs 0-15 */ - stmg %r0, %r15, GEN_LC_SW_INT_GRS - /* save crs 0-15 */ - stctg %c0, %c15, GEN_LC_SW_INT_CRS - /* load a cr0 that has the AFP control bit which enables all FPRs */ - larl %r1, initial_cr0 - lctlg %c0, %c0, 0(%r1) - /* save fprs 0-15 + fpc */ - la %r1, GEN_LC_SW_INT_FPRS - .irp i, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 - std \i, \i * 8(%r1) - .endr - stfpc GEN_LC_SW_INT_FPC - .endm - - .macro RESTORE_REGS - /* restore fprs 0-15 + fpc */ - la %r1, GEN_LC_SW_INT_FPRS - .irp i, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 - ld \i, \i * 8(%r1) - .endr - lfpc GEN_LC_SW_INT_FPC - /* restore crs 0-15 */ - lctlg %c0, %c15, GEN_LC_SW_INT_CRS - /* restore grs 0-15 */ - lmg %r0, %r15, GEN_LC_SW_INT_GRS - .endm - /* Save registers on the stack (r15), so we can have stacked interrupts. */ .macro SAVE_REGS_STACK /* Allocate a full stack frame */