diff mbox series

[v2,3/3] target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU

Message ID 20210216224543.16142-4-rebecca@nuviainc.com (mailing list archive)
State New, archived
Headers show
Series target/arm: Add support for FEAT_SSBS | expand

Commit Message

Rebecca Cran Feb. 16, 2021, 10:45 p.m. UTC 
Enable FEAT_SSBS for the "max" 32-bit CPU.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu.c | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Peter Maydell March 5, 2021, 11:31 a.m. UTC | #1 
On Tue, 16 Feb 2021 at 22:45, Rebecca Cran <rebecca@nuviainc.com> wrote:
>
> Enable FEAT_SSBS for the "max" 32-bit CPU.
>
> Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/cpu.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 5cf6c056c50f..88a6b183d325 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -2206,6 +2206,10 @@ static void arm_max_initfn(Object *obj)
>          t = cpu->isar.id_pfr0;
>          t = FIELD_DP32(t, ID_PFR0, DIT, 1);
>          cpu->isar.id_pfr0 = t;
> +
> +        t = cpu->isar.id_pfr2;
> +        t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
> +        cpu->isar.id_mfr2 = t;

Er, this doesn't compile:

../../target/arm/cpu.c:2223:19: error: no member named 'id_mfr2' in
'struct ARMISARegisters'
        cpu->isar.id_mfr2 = t;
        ~~~~~~~~~ ^

The typo is obvious, so I'm just going to fix it up in the
target-arm queue, but this does suggest that your testing process
before sending out patches could be improved ;-)

thanks
-- PMM
Rebecca Cran March 5, 2021, 3:23 p.m. UTC | #2 
On 3/5/21 4:31 AM, Peter Maydell wrote:
> On Tue, 16 Feb 2021 at 22:45, Rebecca Cran <rebecca@nuviainc.com> wrote:
>>
>> Enable FEAT_SSBS for the "max" 32-bit CPU.
>>
>> Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>>   target/arm/cpu.c | 4 ++++
>>   1 file changed, 4 insertions(+)
>>
>> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
>> index 5cf6c056c50f..88a6b183d325 100644
>> --- a/target/arm/cpu.c
>> +++ b/target/arm/cpu.c
>> @@ -2206,6 +2206,10 @@ static void arm_max_initfn(Object *obj)
>>           t = cpu->isar.id_pfr0;
>>           t = FIELD_DP32(t, ID_PFR0, DIT, 1);
>>           cpu->isar.id_pfr0 = t;
>> +
>> +        t = cpu->isar.id_pfr2;
>> +        t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
>> +        cpu->isar.id_mfr2 = t;
> 
> Er, this doesn't compile:
> 
> ../../target/arm/cpu.c:2223:19: error: no member named 'id_mfr2' in
> 'struct ARMISARegisters'
>          cpu->isar.id_mfr2 = t;
>          ~~~~~~~~~ ^
> 
> The typo is obvious, so I'm just going to fix it up in the
> target-arm queue, but this does suggest that your testing process
> before sending out patches could be improved ;-)

Thanks, and sorry for the mistake. I'll work on improving my testing of 
32-bit ARM targets when I'm making changes to them.
diff mbox series

Patch

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5cf6c056c50f..88a6b183d325 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2206,6 +2206,10 @@  static void arm_max_initfn(Object *obj)
         t = cpu->isar.id_pfr0;
         t = FIELD_DP32(t, ID_PFR0, DIT, 1);
         cpu->isar.id_pfr0 = t;
+
+        t = cpu->isar.id_pfr2;
+        t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
+        cpu->isar.id_mfr2 = t;
     }
 #endif
 }