| Message ID | 20210316101312.102925-8-maz@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | KVM: arm64: Enable SVE support on nVHE systems | expand |
On Tue, Mar 16, 2021 at 10:13:09AM +0000, Marc Zyngier wrote: > Make sure the guest's ZCR_EL1 is saved before we save/flush the > state. This will be useful in later patches. > > Signed-off-by: Marc Zyngier <maz@kernel.org> > --- > arch/arm64/kvm/fpsimd.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c > index 84afca5ed6f2..b5f95abd23f5 100644 > --- a/arch/arm64/kvm/fpsimd.c > +++ b/arch/arm64/kvm/fpsimd.c > @@ -121,10 +121,10 @@ void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu) > local_irq_save(flags); > > if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED) { > - fpsimd_save_and_flush_cpu_state(); > - > if (guest_has_sve) > __vcpu_sys_reg(vcpu, ZCR_EL1) = read_sysreg_el1(SYS_ZCR); > + > + fpsimd_save_and_flush_cpu_state(); I _think_ fpsimd_save_and_flush_cpu_state() contains a RDVL instruction to get at the vector length for sve_get_vl(), and this ends up reading from ZCR_EL1. So I'm not sure it's save to move it like this. Will
On Wed, Mar 17, 2021 at 05:17:38PM +0000, Will Deacon wrote: > On Tue, Mar 16, 2021 at 10:13:09AM +0000, Marc Zyngier wrote: > > Make sure the guest's ZCR_EL1 is saved before we save/flush the > > state. This will be useful in later patches. > > > > Signed-off-by: Marc Zyngier <maz@kernel.org> > > --- > > arch/arm64/kvm/fpsimd.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c > > index 84afca5ed6f2..b5f95abd23f5 100644 > > --- a/arch/arm64/kvm/fpsimd.c > > +++ b/arch/arm64/kvm/fpsimd.c > > @@ -121,10 +121,10 @@ void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu) > > local_irq_save(flags); > > > > if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED) { > > - fpsimd_save_and_flush_cpu_state(); > > - > > if (guest_has_sve) > > __vcpu_sys_reg(vcpu, ZCR_EL1) = read_sysreg_el1(SYS_ZCR); > > + > > + fpsimd_save_and_flush_cpu_state(); > > I _think_ fpsimd_save_and_flush_cpu_state() contains a RDVL instruction > to get at the vector length for sve_get_vl(), and this ends up reading from > ZCR_EL1. So I'm not sure it's save to move it like this. Duh, we're not changing the register here, but just saving it off. So it's fine: Acked-by: Will Deacon <will@kernel.org> Will
diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c index 84afca5ed6f2..b5f95abd23f5 100644 --- a/arch/arm64/kvm/fpsimd.c +++ b/arch/arm64/kvm/fpsimd.c @@ -121,10 +121,10 @@ void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu) local_irq_save(flags); if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED) { - fpsimd_save_and_flush_cpu_state(); - if (guest_has_sve) __vcpu_sys_reg(vcpu, ZCR_EL1) = read_sysreg_el1(SYS_ZCR); + + fpsimd_save_and_flush_cpu_state(); } else if (host_has_sve) { /* * The FPSIMD/SVE state in the CPU has not been touched, and we
Make sure the guest's ZCR_EL1 is saved before we save/flush the state. This will be useful in later patches. Signed-off-by: Marc Zyngier <maz@kernel.org> --- arch/arm64/kvm/fpsimd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)