diff mbox series

[v15,2/2] drm/tegra: dc: Extend debug stats with total number of events

Message ID 20210311172255.25213-3-digetx@gmail.com (mailing list archive)
State Not Applicable, archived
Headers show
Series Add memory bandwidth management to NVIDIA Tegra DRM driver | expand

Commit Message

Dmitry Osipenko March 11, 2021, 5:22 p.m. UTC 
It's useful to know the total number of underflow events and currently
the debug stats are getting reset each time CRTC is being disabled. Let's
account the overall number of events that doesn't get a reset.

Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/gpu/drm/tegra/dc.c | 10 ++++++++++
 drivers/gpu/drm/tegra/dc.h |  5 +++++
 2 files changed, 15 insertions(+)

Comments

Michał Mirosław March 14, 2021, 10:11 p.m. UTC | #1 
On Thu, Mar 11, 2021 at 08:22:55PM +0300, Dmitry Osipenko wrote:
> It's useful to know the total number of underflow events and currently
> the debug stats are getting reset each time CRTC is being disabled. Let's
> account the overall number of events that doesn't get a reset.
[...]

Looks good. It seems independent from the other patch.

Reviewed-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Dmitry Osipenko March 17, 2021, 5:44 p.m. UTC | #2 
15.03.2021 01:11, Michał Mirosław пишет:
> On Thu, Mar 11, 2021 at 08:22:55PM +0300, Dmitry Osipenko wrote:
>> It's useful to know the total number of underflow events and currently
>> the debug stats are getting reset each time CRTC is being disabled. Let's
>> account the overall number of events that doesn't get a reset.
> [...]
> 
> Looks good. It seems independent from the other patch.
> 
> Reviewed-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
> 

This patch was created in order to help with debugging of the bandwidth
management, but technically it's independent. Thank you for the review.
diff mbox series

Patch

diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index 49fa488cf930..ecac28e814ec 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -1539,6 +1539,11 @@  static int tegra_dc_show_stats(struct seq_file *s, void *data)
 	seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
 	seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
 
+	seq_printf(s, "frames total: %lu\n", dc->stats.frames_total);
+	seq_printf(s, "vblank total: %lu\n", dc->stats.vblank_total);
+	seq_printf(s, "underflow total: %lu\n", dc->stats.underflow_total);
+	seq_printf(s, "overflow total: %lu\n", dc->stats.overflow_total);
+
 	return 0;
 }
 
@@ -2313,6 +2318,7 @@  static irqreturn_t tegra_dc_irq(int irq, void *data)
 		/*
 		dev_dbg(dc->dev, "%s(): frame end\n", __func__);
 		*/
+		dc->stats.frames_total++;
 		dc->stats.frames++;
 	}
 
@@ -2321,6 +2327,7 @@  static irqreturn_t tegra_dc_irq(int irq, void *data)
 		dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
 		*/
 		drm_crtc_handle_vblank(&dc->base);
+		dc->stats.vblank_total++;
 		dc->stats.vblank++;
 	}
 
@@ -2328,6 +2335,7 @@  static irqreturn_t tegra_dc_irq(int irq, void *data)
 		/*
 		dev_dbg(dc->dev, "%s(): underflow\n", __func__);
 		*/
+		dc->stats.underflow_total++;
 		dc->stats.underflow++;
 	}
 
@@ -2335,11 +2343,13 @@  static irqreturn_t tegra_dc_irq(int irq, void *data)
 		/*
 		dev_dbg(dc->dev, "%s(): overflow\n", __func__);
 		*/
+		dc->stats.overflow_total++;
 		dc->stats.overflow++;
 	}
 
 	if (status & HEAD_UF_INT) {
 		dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__);
+		dc->stats.underflow_total++;
 		dc->stats.underflow++;
 	}
 
diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h
index 69d4cca2e58c..ad8d51a55a00 100644
--- a/drivers/gpu/drm/tegra/dc.h
+++ b/drivers/gpu/drm/tegra/dc.h
@@ -48,6 +48,11 @@  struct tegra_dc_stats {
 	unsigned long vblank;
 	unsigned long underflow;
 	unsigned long overflow;
+
+	unsigned long frames_total;
+	unsigned long vblank_total;
+	unsigned long underflow_total;
+	unsigned long overflow_total;
 };
 
 struct tegra_windowgroup_soc {