| Message ID | 1616046056-29068-2-git-send-email-rex-bc.chen@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add check for max clock rate in mode_valid | expand |
Hi Rex-BC Chen, Thank you for your patch. Missatge de Rex-BC Chen <rex-bc.chen@mediatek.com> del dia dj., 18 de març 2021 a les 6:42: > > Add per-platform max clock rate check in mtk_dpi_bridge_mode_valid. > > Signed-off-by: Pi-Hsun Shih <pihsun@chromium.org> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_dpi.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c > index b05f900d9322..0b427ad0cd9b 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > @@ -120,6 +120,7 @@ struct mtk_dpi_yc_limit { > struct mtk_dpi_conf { > unsigned int (*cal_factor)(int clock); > u32 reg_h_fre_con; > + u32 max_clock_khz; > bool edge_sel_en; > }; > > @@ -557,9 +558,23 @@ static void mtk_dpi_bridge_enable(struct drm_bridge *bridge) > mtk_dpi_set_display_mode(dpi, &dpi->mode); > } > > +static enum drm_mode_status > +mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge, > + const struct drm_display_info *info, > + const struct drm_display_mode *mode) > +{ > + struct mtk_dpi *dpi = bridge_to_dpi(bridge); > + > + if (dpi->conf->max_clock_khz && mode->clock > dpi->conf->max_clock_khz) Maybe I read this patch too fast, but why the &&? Shouldn't be more simple and readable if (mode->clock > max_clock) Thanks, Enric > + return MODE_CLOCK_HIGH; > + > + return MODE_OK; > +} > + > static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = { > .attach = mtk_dpi_bridge_attach, > .mode_set = mtk_dpi_bridge_mode_set, > + .mode_valid = mtk_dpi_bridge_mode_valid, > .disable = mtk_dpi_bridge_disable, > .enable = mtk_dpi_bridge_enable, > }; > @@ -668,17 +683,20 @@ static unsigned int mt8183_calculate_factor(int clock) > static const struct mtk_dpi_conf mt8173_conf = { > .cal_factor = mt8173_calculate_factor, > .reg_h_fre_con = 0xe0, > + .max_clock_khz = 300000, > }; > > static const struct mtk_dpi_conf mt2701_conf = { > .cal_factor = mt2701_calculate_factor, > .reg_h_fre_con = 0xb0, > .edge_sel_en = true, > + .max_clock_khz = 150000, > }; > > static const struct mtk_dpi_conf mt8183_conf = { > .cal_factor = mt8183_calculate_factor, > .reg_h_fre_con = 0xe0, > + .max_clock_khz = 100000, > }; > > static int mtk_dpi_probe(struct platform_device *pdev) > -- > 2.18.0 > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek
Hi, Enric: Enric Balletbo Serra <eballetbo@gmail.com> 於 2021年3月18日 週四 下午10:25寫道： > > Hi Rex-BC Chen, > > Thank you for your patch. > > Missatge de Rex-BC Chen <rex-bc.chen@mediatek.com> del dia dj., 18 de > març 2021 a les 6:42: > > > > Add per-platform max clock rate check in mtk_dpi_bridge_mode_valid. > > > > Signed-off-by: Pi-Hsun Shih <pihsun@chromium.org> > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> > > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_dpi.c | 18 ++++++++++++++++++ > > 1 file changed, 18 insertions(+) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c > > index b05f900d9322..0b427ad0cd9b 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > > @@ -120,6 +120,7 @@ struct mtk_dpi_yc_limit { > > struct mtk_dpi_conf { > > unsigned int (*cal_factor)(int clock); > > u32 reg_h_fre_con; > > + u32 max_clock_khz; > > bool edge_sel_en; > > }; > > > > @@ -557,9 +558,23 @@ static void mtk_dpi_bridge_enable(struct drm_bridge *bridge) > > mtk_dpi_set_display_mode(dpi, &dpi->mode); > > } > > > > +static enum drm_mode_status > > +mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge, > > + const struct drm_display_info *info, > > + const struct drm_display_mode *mode) > > +{ > > + struct mtk_dpi *dpi = bridge_to_dpi(bridge); > > + > > + if (dpi->conf->max_clock_khz && mode->clock > dpi->conf->max_clock_khz) > > Maybe I read this patch too fast, but why the &&? Shouldn't be more > simple and readable > > if (mode->clock > max_clock) > Agree. So I modify in mediatek-drm-next [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next Regards, Chun-Kuang. > Thanks, > Enric > > > > + return MODE_CLOCK_HIGH; > > + > > + return MODE_OK; > > +} > > + > > static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = { > > .attach = mtk_dpi_bridge_attach, > > .mode_set = mtk_dpi_bridge_mode_set, > > + .mode_valid = mtk_dpi_bridge_mode_valid, > > .disable = mtk_dpi_bridge_disable, > > .enable = mtk_dpi_bridge_enable, > > }; > > @@ -668,17 +683,20 @@ static unsigned int mt8183_calculate_factor(int clock) > > static const struct mtk_dpi_conf mt8173_conf = { > > .cal_factor = mt8173_calculate_factor, > > .reg_h_fre_con = 0xe0, > > + .max_clock_khz = 300000, > > }; > > > > static const struct mtk_dpi_conf mt2701_conf = { > > .cal_factor = mt2701_calculate_factor, > > .reg_h_fre_con = 0xb0, > > .edge_sel_en = true, > > + .max_clock_khz = 150000, > > }; > > > > static const struct mtk_dpi_conf mt8183_conf = { > > .cal_factor = mt8183_calculate_factor, > > .reg_h_fre_con = 0xe0, > > + .max_clock_khz = 100000, > > }; > > > > static int mtk_dpi_probe(struct platform_device *pdev) > > -- > > 2.18.0 > > _______________________________________________ > > Linux-mediatek mailing list > > Linux-mediatek@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-mediatek
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index b05f900d9322..0b427ad0cd9b 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -120,6 +120,7 @@ struct mtk_dpi_yc_limit { struct mtk_dpi_conf { unsigned int (*cal_factor)(int clock); u32 reg_h_fre_con; + u32 max_clock_khz; bool edge_sel_en; }; @@ -557,9 +558,23 @@ static void mtk_dpi_bridge_enable(struct drm_bridge *bridge) mtk_dpi_set_display_mode(dpi, &dpi->mode); } +static enum drm_mode_status +mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + struct mtk_dpi *dpi = bridge_to_dpi(bridge); + + if (dpi->conf->max_clock_khz && mode->clock > dpi->conf->max_clock_khz) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = { .attach = mtk_dpi_bridge_attach, .mode_set = mtk_dpi_bridge_mode_set, + .mode_valid = mtk_dpi_bridge_mode_valid, .disable = mtk_dpi_bridge_disable, .enable = mtk_dpi_bridge_enable, }; @@ -668,17 +683,20 @@ static unsigned int mt8183_calculate_factor(int clock) static const struct mtk_dpi_conf mt8173_conf = { .cal_factor = mt8173_calculate_factor, .reg_h_fre_con = 0xe0, + .max_clock_khz = 300000, }; static const struct mtk_dpi_conf mt2701_conf = { .cal_factor = mt2701_calculate_factor, .reg_h_fre_con = 0xb0, .edge_sel_en = true, + .max_clock_khz = 150000, }; static const struct mtk_dpi_conf mt8183_conf = { .cal_factor = mt8183_calculate_factor, .reg_h_fre_con = 0xe0, + .max_clock_khz = 100000, }; static int mtk_dpi_probe(struct platform_device *pdev)