diff mbox series

[V2,2/2] arm64: dts: qcom: sc7180: Remove QUP-CORE ICC path

Message ID 20210318111009.30365-3-rojay@codeaurora.org (mailing list archive)
State Superseded
Headers show
Series Separate out earlycon | expand

Commit Message

Roja Rani Yarubandi March 18, 2021, 11:10 a.m. UTC 
We had introduced the QUP-CORE ICC path to put proxy votes from
QUP wrapper on behalf of earlycon, if other users of QUP-CORE turn
off this clock before the real console is probed, unclocked access
to HW was seen from earlycon.

With ICC sync state support proxy votes are no longer need as ICC
will ensure that the default bootloader votes are not removed until
all it's consumer are probed.

We can safely remove ICC path for QUP-CORE clock from QUP wrapper
device.

Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
---
Changes in V2:
 - No chage

 arch/arm64/boot/dts/qcom/sc7180.dtsi | 4 ----
 1 file changed, 4 deletions(-)

Comments

Matthias Kaehlcke March 18, 2021, 5:17 p.m. UTC | #1 
On Thu, Mar 18, 2021 at 04:40:09PM +0530, Roja Rani Yarubandi wrote:
> We had introduced the QUP-CORE ICC path to put proxy votes from
> QUP wrapper on behalf of earlycon, if other users of QUP-CORE turn
> off this clock before the real console is probed, unclocked access
> to HW was seen from earlycon.
> 
> With ICC sync state support proxy votes are no longer need as ICC
> will ensure that the default bootloader votes are not removed until
> all it's consumer are probed.
> 
> We can safely remove ICC path for QUP-CORE clock from QUP wrapper
> device.
> 
> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
> Signed-off-by: Akash Asthana <akashast@codeaurora.org>

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 83fbb481cae5..2709051740d1 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -768,8 +768,6 @@  qupv3_id_0: geniqup@8c0000 {
 			#size-cells = <2>;
 			ranges;
 			iommus = <&apps_smmu 0x43 0x0>;
-			interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>;
-			interconnect-names = "qup-core";
 			status = "disabled";
 
 			i2c0: i2c@880000 {
@@ -1059,8 +1057,6 @@  qupv3_id_1: geniqup@ac0000 {
 			#size-cells = <2>;
 			ranges;
 			iommus = <&apps_smmu 0x4c3 0x0>;
-			interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>;
-			interconnect-names = "qup-core";
 			status = "disabled";
 
 			i2c6: i2c@a80000 {