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[net-next,0/8] configuration support for switch headers & phy

Message ID 20210321120958.17531-1-hkelam@marvell.com (mailing list archive)
Headers show
Series configuration support for switch headers & phy | expand

Message

Hariprasad Kelam March 21, 2021, 12:09 p.m. UTC 
This series of patches add support for parsing switch headers and
configuration support for phy modulation type(NRZ or PAM4).

PHYs that support changing modulation type ,user can configure it
through private flags pam4.

Marvell switches support DSA(distributed switch architecture) with
different switch headers like FDSA and EDSA. This patch series adds
private flags to enable user to configure interface in fdsa/edsa
mode such that flow steering (forwading packets to pf/vf depending on
switch header fields) and packet parsing can be acheived.

Also adds support for HIGIG2 protocol, user can configure interface
in higig mode through higig private flage, such that packet classification
and flow sterring achieved on packets with higig header


Felix Manlunas (2):
  octeontx2-af: Add new CGX_CMDs to set and get PHY modulation type
  octeontx2-pf: Add ethtool priv flag to control PAM4 on/off

Hariprasad Kelam (6):
  octeontx2-af: Support for parsing pkts with switch headers
  octeontx2-af: Do not allow VFs to overwrite PKIND config
  octeontx2-af: Put CGX LMAC also in Higig2 mode
  octeontx2-pf: Support to enable EDSA/Higig2 pkts parsing
  octeontx2-af: Add flow steering support for FDSA tag
  octeontx2-pf: Add ntuple filter support for FDSA

 .../net/ethernet/marvell/octeontx2/af/cgx.c   | 177 ++++++++++++-
 .../net/ethernet/marvell/octeontx2/af/cgx.h   |  19 +-
 .../ethernet/marvell/octeontx2/af/cgx_fw_if.h |   6 +
 .../net/ethernet/marvell/octeontx2/af/mbox.h  |  39 ++-
 .../net/ethernet/marvell/octeontx2/af/npc.h   |  14 +-
 .../net/ethernet/marvell/octeontx2/af/rvu.h   |   9 +
 .../ethernet/marvell/octeontx2/af/rvu_cgx.c   | 103 +++++++-
 .../marvell/octeontx2/af/rvu_debugfs.c        |   3 +-
 .../ethernet/marvell/octeontx2/af/rvu_nix.c   |  44 +++-
 .../ethernet/marvell/octeontx2/af/rvu_npc.c   |  76 ++++++
 .../marvell/octeontx2/af/rvu_npc_fs.c         |  14 +-
 .../marvell/octeontx2/nic/otx2_common.c       |   2 +
 .../marvell/octeontx2/nic/otx2_common.h       |  36 ++-
 .../marvell/octeontx2/nic/otx2_ethtool.c      | 244 ++++++++++++++++++
 .../marvell/octeontx2/nic/otx2_flows.c        |  58 ++++-
 .../ethernet/marvell/octeontx2/nic/otx2_pf.c  |  21 +-
 .../marvell/octeontx2/nic/otx2_txrx.c         |   1 +
 .../ethernet/marvell/octeontx2/nic/otx2_vf.c  |  10 +
 18 files changed, 832 insertions(+), 44 deletions(-)

--
2.17.1

Comments

Andrew Lunn March 21, 2021, 2:15 p.m. UTC | #1 
On Sun, Mar 21, 2021 at 05:39:50PM +0530, Hariprasad Kelam wrote:
> This series of patches add support for parsing switch headers and
> configuration support for phy modulation type(NRZ or PAM4).
> 
> PHYs that support changing modulation type ,user can configure it
> through private flags pam4.
> 
> Marvell switches support DSA(distributed switch architecture) with
> different switch headers like FDSA and EDSA. This patch series adds
> private flags to enable user to configure interface in fdsa/edsa
> mode such that flow steering (forwading packets to pf/vf depending on
> switch header fields) and packet parsing can be acheived.

Hi Hariprasad 

Private flags sound very wrong here. I would expect to see some
integration between the switchdev/DSA driver and the MAC driver.
Please show how this works in combination with
drivers/net/dsa/mv88e6xxx or drivers/net/ethernet/marvell/prestera.

	  Andrew