| Message ID | 1616567465-153141-1-git-send-email-robert.hu@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] i386/cpu_dump: support AVX512 ZMM regs dump | expand |
Patchew URL: https://patchew.org/QEMU/1616567465-153141-1-git-send-email-robert.hu@linux.intel.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1616567465-153141-1-git-send-email-robert.hu@linux.intel.com
Subject: [PATCH v2] i386/cpu_dump: support AVX512 ZMM regs dump
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/1616567465-153141-1-git-send-email-robert.hu@linux.intel.com -> patchew/1616567465-153141-1-git-send-email-robert.hu@linux.intel.com
- [tag update] patchew/20210323155132.238193-1-f4bug@amsat.org -> patchew/20210323155132.238193-1-f4bug@amsat.org
- [tag update] patchew/20210323165308.15244-1-alex.bennee@linaro.org -> patchew/20210323165308.15244-1-alex.bennee@linaro.org
- [tag update] patchew/91d5978357fb8709ef61d2030984f7142847037d.1616141556.git.huangy81@chinatelecom.cn -> patchew/91d5978357fb8709ef61d2030984f7142847037d.1616141556.git.huangy81@chinatelecom.cn
Switched to a new branch 'test'
34024e2 i386/cpu_dump: support AVX512 ZMM regs dump
=== OUTPUT BEGIN ===
ERROR: else should follow close brace '}'
#64: FILE: target/i386/cpu-dump.c:520:
+ }
+ else if (env->xcr0 & XFEATURE_AVX) {
ERROR: else should follow close brace '}'
#76: FILE: target/i386/cpu-dump.c:532:
+ }
+ else { /* SSE and below cases */
ERROR: spaces required around that '|' (ctx:VxE)
#106: FILE: target/i386/cpu.h:259:
+ XFEATURE_AVX512_ZMM_Hi256| \
^
total: 3 errors, 0 warnings, 80 lines checked
Commit 34024e2b18d2 (i386/cpu_dump: support AVX512 ZMM regs dump) has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/1616567465-153141-1-git-send-email-robert.hu@linux.intel.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
diff --git a/target/i386/cpu-dump.c b/target/i386/cpu-dump.c index aac21f1..c130586 100644 --- a/target/i386/cpu-dump.c +++ b/target/i386/cpu-dump.c @@ -499,21 +499,48 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags) else qemu_fprintf(f, " "); } - if (env->hflags & HF_CS64_MASK) - nb = 16; - else - nb = 8; - for(i=0;i<nb;i++) { - qemu_fprintf(f, "XMM%02d=%08x%08x%08x%08x", - i, - env->xmm_regs[i].ZMM_L(3), - env->xmm_regs[i].ZMM_L(2), - env->xmm_regs[i].ZMM_L(1), - env->xmm_regs[i].ZMM_L(0)); - if ((i & 1) == 1) - qemu_fprintf(f, "\n"); - else - qemu_fprintf(f, " "); + + if ((env->xcr0 & XFEATURE_AVX512) == XFEATURE_AVX512) { + /* XSAVE enabled AVX512 */ + nb = (env->hflags & HF_CS64_MASK) ? 32 : 8; + for (i = 0; i < nb; i++) { + qemu_fprintf(f, "ZMM%02d=0x%016lx %016lx %016lx %016lx %016lx " + "%016lx %016lx %016lx\n", + i, + env->xmm_regs[i].ZMM_Q(7), + env->xmm_regs[i].ZMM_Q(6), + env->xmm_regs[i].ZMM_Q(5), + env->xmm_regs[i].ZMM_Q(4), + env->xmm_regs[i].ZMM_Q(3), + env->xmm_regs[i].ZMM_Q(2), + env->xmm_regs[i].ZMM_Q(1), + env->xmm_regs[i].ZMM_Q(0)); + } + } + else if (env->xcr0 & XFEATURE_AVX) { + /* XSAVE enabled AVX */ + nb = env->hflags & HF_CS64_MASK ? 16 : 8; + for (i = 0; i < nb; i++) { + qemu_fprintf(f, "YMM%02d=0x%016lx %016lx %016lx %016lx\n", + i, + env->xmm_regs[i].ZMM_Q(3), + env->xmm_regs[i].ZMM_Q(2), + env->xmm_regs[i].ZMM_Q(1), + env->xmm_regs[i].ZMM_Q(0)); + } + } + else { /* SSE and below cases */ + nb = env->hflags & HF_CS64_MASK ? 16 : 8; + for (i = 0; i < nb; i++) { + qemu_fprintf(f, "XMM%02d=0x%016lx %016lx", + i, + env->xmm_regs[i].ZMM_Q(1), + env->xmm_regs[i].ZMM_Q(0)); + if ((i & 1) == 1) + qemu_fprintf(f, "\n"); + else + qemu_fprintf(f, " "); + } } } if (flags & CPU_DUMP_CODE) { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 570f916..a011702 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -249,6 +249,17 @@ typedef enum X86Seg { #define CR4_PKE_MASK (1U << 22) #define CR4_PKS_MASK (1U << 24) +#define XFEATURE_X87 (1UL << 0) +#define XFEATURE_SSE (1UL << 1) +#define XFEATURE_AVX (1UL << 2) +#define XFEATURE_AVX512_OPMASK (1UL << 5) +#define XFEATURE_AVX512_ZMM_Hi256 (1UL << 6) +#define XFEATURE_AVX512_Hi16_ZMM (1UL << 7) +#define XFEATURE_AVX512 (XFEATURE_AVX512_OPMASK | \ + XFEATURE_AVX512_ZMM_Hi256| \ + XFEATURE_AVX512_Hi16_ZMM) + + #define DR6_BD (1 << 13) #define DR6_BS (1 << 14) #define DR6_BT (1 << 15)
Since commit fa4518741e (target-i386: Rename struct XMMReg to ZMMReg), CPUX86State.xmm_regs[] has already been extended to 512bit to support AVX512. Also, other qemu level supports for AVX512 registers are there for years. But in x86_cpu_dump_state(), still only dump XMM registers no matter YMM/ZMM is enabled. This patch is to complement this, let it dump XMM/YMM/ZMM accordingly. Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> --- Changelog: v2: dump XMM/YMM/ZMM according to XSAVE state-components enablement. target/i386/cpu-dump.c | 57 +++++++++++++++++++++++++++++++++++++------------- target/i386/cpu.h | 11 ++++++++++ 2 files changed, 53 insertions(+), 15 deletions(-)