diff mbox series

[net] amd-xgbe: Update DMA coherency values

Message ID 20210325030912.2541181-1-Shyam-sundar.S-k@amd.com (mailing list archive)
State Accepted
Commit d75135082698140a26a56defe1bbc1b06f26a41f
Delegated to: Netdev Maintainers
Headers show
Series [net] amd-xgbe: Update DMA coherency values | expand

Checks

Context Check Description
netdev/cover_letter success Link
netdev/fixes_present success Link
netdev/patch_count success Link
netdev/tree_selection success Clearly marked for net
netdev/subject_prefix success Link
netdev/cc_maintainers success CCed 4 of 4 maintainers
netdev/source_inline success Was 0 now: 0
netdev/verify_signedoff success Link
netdev/module_param success Was 0 now: 0
netdev/build_32bit success Errors and warnings before: 0 this patch: 0
netdev/kdoc success Errors and warnings before: 0 this patch: 0
netdev/verify_fixes success Link
netdev/checkpatch success total: 0 errors, 0 warnings, 0 checks, 12 lines checked
netdev/build_allmodconfig_warn success Errors and warnings before: 0 this patch: 0
netdev/header_inline success Link

Commit Message

Shyam Sundar S K March 25, 2021, 3:09 a.m. UTC
Based on the IOMMU configuration, the current cache control settings can
result in possible coherency issues. The hardware team has recommended
new settings for the PCI device path to eliminate the issue.

Fixes: 6f595959c095 ("amd-xgbe: Adjust register settings to improve performance")
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
---

Please queue this patch up for stable, 4.14 and higher.

 drivers/net/ethernet/amd/xgbe/xgbe.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Comments

Tom Lendacky March 25, 2021, 1:51 p.m. UTC | #1
On 3/24/21 10:09 PM, Shyam Sundar S K wrote:
> Based on the IOMMU configuration, the current cache control settings can
> result in possible coherency issues. The hardware team has recommended
> new settings for the PCI device path to eliminate the issue.
> 
> Fixes: 6f595959c095 ("amd-xgbe: Adjust register settings to improve performance")
> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>

Acked-by: Tom Lendacky <thomas.lendacky@amd.com>

> ---
> 
> Please queue this patch up for stable, 4.14 and higher.
> 
>  drivers/net/ethernet/amd/xgbe/xgbe.h | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h
> index ba8321ec1ee7..3305979a9f7c 100644
> --- a/drivers/net/ethernet/amd/xgbe/xgbe.h
> +++ b/drivers/net/ethernet/amd/xgbe/xgbe.h
> @@ -180,9 +180,9 @@
>  #define XGBE_DMA_SYS_AWCR	0x30303030
>  
>  /* DMA cache settings - PCI device */
> -#define XGBE_DMA_PCI_ARCR	0x00000003
> -#define XGBE_DMA_PCI_AWCR	0x13131313
> -#define XGBE_DMA_PCI_AWARCR	0x00000313
> +#define XGBE_DMA_PCI_ARCR	0x000f0f0f
> +#define XGBE_DMA_PCI_AWCR	0x0f0f0f0f
> +#define XGBE_DMA_PCI_AWARCR	0x00000f0f
>  
>  /* DMA channel interrupt modes */
>  #define XGBE_IRQ_MODE_EDGE	0
>
patchwork-bot+netdevbpf@kernel.org March 26, 2021, 12:30 a.m. UTC | #2
Hello:

This patch was applied to netdev/net.git (refs/heads/master):

On Thu, 25 Mar 2021 08:39:12 +0530 you wrote:
> Based on the IOMMU configuration, the current cache control settings can
> result in possible coherency issues. The hardware team has recommended
> new settings for the PCI device path to eliminate the issue.
> 
> Fixes: 6f595959c095 ("amd-xgbe: Adjust register settings to improve performance")
> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
> 
> [...]

Here is the summary with links:
  - [net] amd-xgbe: Update DMA coherency values
    https://git.kernel.org/netdev/net/c/d75135082698

You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
diff mbox series

Patch

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h
index ba8321ec1ee7..3305979a9f7c 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe.h
+++ b/drivers/net/ethernet/amd/xgbe/xgbe.h
@@ -180,9 +180,9 @@ 
 #define XGBE_DMA_SYS_AWCR	0x30303030
 
 /* DMA cache settings - PCI device */
-#define XGBE_DMA_PCI_ARCR	0x00000003
-#define XGBE_DMA_PCI_AWCR	0x13131313
-#define XGBE_DMA_PCI_AWARCR	0x00000313
+#define XGBE_DMA_PCI_ARCR	0x000f0f0f
+#define XGBE_DMA_PCI_AWCR	0x0f0f0f0f
+#define XGBE_DMA_PCI_AWARCR	0x00000f0f
 
 /* DMA channel interrupt modes */
 #define XGBE_IRQ_MODE_EDGE	0