diff mbox series

[v2,2/2] arm64: dts: renesas: r8a779a0: Add VSPD support

Message ID 20210322172919.1154686-3-kieran.bingham+renesas@ideasonboard.com (mailing list archive)
State Mainlined
Commit 7c4721276611800681f14e1e54dea01ddcc6c429
Delegated to: Geert Uytterhoeven
Headers show
Series arm64: dts: renesas: r8a779a0: Add VSP support | expand

Commit Message

Kieran Bingham March 22, 2021, 5:29 p.m. UTC 
Provide VSPD support on the V3U.

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
---
 arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

Comments

Geert Uytterhoeven March 29, 2021, 7:40 a.m. UTC | #1 
On Mon, Mar 22, 2021 at 6:29 PM Kieran Bingham
<kieran.bingham+renesas@ideasonboard.com> wrote:
> Provide VSPD support on the V3U.
>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.13.

Gr{oetje,eeting}s,

                        Geert
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
index 73036a5b8312..52a48e8d5814 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
@@ -1118,6 +1118,28 @@  fcpvd1: fcp@fea11000 {
 			resets = <&cpg 509>;
 		};
 
+		vspd0: vsp@fea20000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfea20000 0 0x5000>;
+			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 830>;
+			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+			resets = <&cpg 830>;
+
+			renesas,fcp = <&fcpvd0>;
+		};
+
+		vspd1: vsp@fea28000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfea28000 0 0x5000>;
+			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 831>;
+			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+			resets = <&cpg 831>;
+
+			renesas,fcp = <&fcpvd1>;
+		};
+
 		prr: chipid@fff00044 {
 			compatible = "renesas,prr";
 			reg = <0 0xfff00044 0 4>;