| Message ID | 20210202005948.241655-1-ben.widawsky@intel.com |
|---|---|
| Headers | show |
| Series | CXL 2.0 Support | expand |
Patchew URL: https://patchew.org/QEMU/20210202005948.241655-1-ben.widawsky@intel.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210202005948.241655-1-ben.widawsky@intel.com
Subject: [RFC PATCH v3 00/31] CXL 2.0 Support
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/20210202005948.241655-1-ben.widawsky@intel.com -> patchew/20210202005948.241655-1-ben.widawsky@intel.com
Switched to a new branch 'test'
e26ed22 WIP: i386/cxl: Initialize a host bridge
9329c2b qtest/cxl: Add very basic sanity tests
c140fd9 hw/cxl/device: Implement get/set LSA
8ed7755 hw/cxl/device: Plumb real LSA sizing
5f683ab hw/cxl/device: Add some trivial commands
4399501 tests/acpi: Add new CEDT files
6c13c92 acpi/cxl: Create the CEDT (9.14.1)
04a874a tests/acpi: allow CEDT table addition
50f82e6 acpi/cxl: Add _OSC implementation (9.14.2)
7eb8038 hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12)
ba80470 hw/cxl/device: Add a memory device (8.2.8.5)
54b9662 hw/cxl/rp: Add a root port
e70de08 hw/pxb/cxl: Add "windows" for host bridges
606831a acpi/pxb/cxl: Reserve host bridge MMIO
29a562b hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142)
32e7bdd hw/pci: Plumb _UID through host bridges
6651f84 tests/acpi: remove stale allowed tables
24837fc acpi/pci: Consolidate host bridge setup
52f548c qtest: allow DSDT acpi table changes
bdcd7d9 hw/pxb: Allow creation of a CXL PXB (host bridge)
5d67d7e hw/pci/cxl: Create a CXL bus type
3b0d310 hw/pxb: Use a type for realizing expanders
5ccf850 hw/cxl/device: Add log commands (8.2.9.4) + CEL
892e722 hw/cxl/device: Timestamp implementation (8.2.9.3)
f2444bb hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1)
67fa438 hw/cxl/device: Add memory device utilities
cfa875c hw/cxl/device: Implement basic mailbox (8.2.8.4)
bdd7975 hw/cxl/device: Implement the CAP array (8.2.8.1-2)
c9e87d1 hw/cxl/device: Introduce a CXL device (8.2.8)
1cc9e2a hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)
7b0e042 hw/pci/cxl: Add a CXL component type (interface)
=== OUTPUT BEGIN ===
1/31 Checking commit 7b0e042bc22b (hw/pci/cxl: Add a CXL component type (interface))
2/31 Checking commit 1cc9e2a0a6d5 (hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5))
WARNING: line over 80 characters
#187: FILE: hw/cxl/cxl-component-utils.c:101:
+ reg_state[R_CXL_RAS_ERR_CAP_CTRL] = 0; /* CXL switches and devices must set */
WARNING: line over 80 characters
#193: FILE: hw/cxl/cxl-component-utils.c:107:
+ ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_GLOBAL_CONTROL, HDM_DECODER_ENABLE, 0);
WARNING: line over 80 characters
#406: FILE: include/hw/cxl/cxl_component.h:62:
+#define CXL_RAS_REGISTERS_OFFSET 0x80 /* Give ample space for caps before this */
WARNING: line over 80 characters
#417: FILE: include/hw/cxl/cxl_component.h:73:
+#define CXL_SEC_REGISTERS_OFFSET (CXL_RAS_REGISTERS_OFFSET + CXL_RAS_REGISTERS_SIZE)
WARNING: line over 80 characters
#421: FILE: include/hw/cxl/cxl_component.h:77:
+#define CXL_LINK_REGISTERS_OFFSET (CXL_SEC_REGISTERS_OFFSET + CXL_SEC_REGISTERS_SIZE)
WARNING: line over 80 characters
#465: FILE: include/hw/cxl/cxl_component.h:121:
+#define CXL_EXTSEC_REGISTERS_OFFSET (CXL_HDM_REGISTERS_OFFSET + CXL_HDM_REGISTERS_SIZE)
WARNING: line over 80 characters
#469: FILE: include/hw/cxl/cxl_component.h:125:
+#define CXL_IDE_REGISTERS_OFFSET (CXL_EXTSEC_REGISTERS_OFFSET + CXL_EXTSEC_REGISTERS_SIZE)
WARNING: line over 80 characters
#473: FILE: include/hw/cxl/cxl_component.h:129:
+#define CXL_SNOOP_REGISTERS_OFFSET (CXL_IDE_REGISTERS_OFFSET + CXL_IDE_REGISTERS_SIZE)
total: 0 errors, 8 warnings, 582 lines checked
Patch 2/31 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/31 Checking commit c9e87d150708 (hw/cxl/device: Introduce a CXL device (8.2.8))
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#36:
new file mode 100644
WARNING: line over 80 characters
#156: FILE: include/hw/cxl/cxl_device.h:116:
+#define CXL_DEVICE_CAPABILITY_HEADER_REGISTER(n, offset) \
total: 0 errors, 2 warnings, 162 lines checked
Patch 3/31 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
4/31 Checking commit bdd7975aa4bc (hw/cxl/device: Implement the CAP array (8.2.8.1-2))
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#23:
new file mode 100644
ERROR: Macros with complex values should be enclosed in parenthesis
#159: FILE: include/hw/cxl/cxl_device.h:75:
+#define CXL_MMIO_SIZE \
+ CXL_DEVICE_CAP_REG_SIZE + CXL_DEVICE_REGISTERS_LENGTH + \
+ CXL_MAILBOX_REGISTERS_LENGTH
WARNING: line over 80 characters
#179: FILE: include/hw/cxl/cxl_device.h:138:
+#define cxl_device_cap_init(dstate, reg, cap_id) \
WARNING: line over 80 characters
#180: FILE: include/hw/cxl/cxl_device.h:139:
+ do { \
WARNING: line over 80 characters
#181: FILE: include/hw/cxl/cxl_device.h:140:
+ uint32_t *cap_hdrs = dstate->caps_reg_state32; \
WARNING: line over 80 characters
#182: FILE: include/hw/cxl/cxl_device.h:141:
+ int which = R_CXL_DEV_##reg##_CAP_HDR0; \
WARNING: line over 80 characters
#183: FILE: include/hw/cxl/cxl_device.h:142:
+ cap_hdrs[which] = \
WARNING: line over 80 characters
#184: FILE: include/hw/cxl/cxl_device.h:143:
+ FIELD_DP32(cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, CAP_ID, cap_id); \
WARNING: line over 80 characters
#185: FILE: include/hw/cxl/cxl_device.h:144:
+ cap_hdrs[which] = FIELD_DP32( \
WARNING: line over 80 characters
#186: FILE: include/hw/cxl/cxl_device.h:145:
+ cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, CAP_VERSION, 1); \
WARNING: line over 80 characters
#187: FILE: include/hw/cxl/cxl_device.h:146:
+ cap_hdrs[which + 1] = \
WARNING: line over 80 characters
#188: FILE: include/hw/cxl/cxl_device.h:147:
+ FIELD_DP32(cap_hdrs[which + 1], CXL_DEV_##reg##_CAP_HDR1, \
WARNING: line over 80 characters
#189: FILE: include/hw/cxl/cxl_device.h:148:
+ CAP_OFFSET, CXL_##reg##_REGISTERS_OFFSET); \
WARNING: line over 80 characters
#190: FILE: include/hw/cxl/cxl_device.h:149:
+ cap_hdrs[which + 2] = \
WARNING: line over 80 characters
#191: FILE: include/hw/cxl/cxl_device.h:150:
+ FIELD_DP32(cap_hdrs[which + 2], CXL_DEV_##reg##_CAP_HDR2, \
WARNING: line over 80 characters
#192: FILE: include/hw/cxl/cxl_device.h:151:
+ CAP_LENGTH, CXL_##reg##_REGISTERS_LENGTH); \
total: 1 errors, 15 warnings, 158 lines checked
Patch 4/31 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/31 Checking commit cfa875c3c48b (hw/cxl/device: Implement basic mailbox (8.2.8.4))
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#191:
new file mode 100644
ERROR: space prohibited between function name and open parenthesis '('
#264: FILE: hw/cxl/cxl-mailbox-utils.c:69:
+typedef ret_code (*opcode_handler)(struct cxl_cmd *cmd,
total: 1 errors, 1 warnings, 416 lines checked
Patch 5/31 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/31 Checking commit 67fa4383326f (hw/cxl/device: Add memory device utilities)
7/31 Checking commit f2444bba9cd7 (hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1))
8/31 Checking commit 892e722ede17 (hw/cxl/device: Timestamp implementation (8.2.9.3))
9/31 Checking commit 5ccf850db462 (hw/cxl/device: Add log commands (8.2.9.4) + CEL)
10/31 Checking commit 3b0d3108b26c (hw/pxb: Use a type for realizing expanders)
11/31 Checking commit 5d67d7eb3d82 (hw/pci/cxl: Create a CXL bus type)
12/31 Checking commit bdcd7d995e9f (hw/pxb: Allow creation of a CXL PXB (host bridge))
13/31 Checking commit 52f548ca385d (qtest: allow DSDT acpi table changes)
14/31 Checking commit 24837fc1bb0e (acpi/pci: Consolidate host bridge setup)
15/31 Checking commit 6651f845de76 (tests/acpi: remove stale allowed tables)
16/31 Checking commit 32e7bdd7607d (hw/pci: Plumb _UID through host bridges)
WARNING: line over 80 characters
#113: FILE: hw/pci-bridge/pci_expander_bridge.c:422:
+ error_setg(errp, "pxb-cxl devices must have a valid uid (0-2147483647)");
total: 0 errors, 1 warnings, 113 lines checked
Patch 16/31 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/31 Checking commit 29a562ba112f (hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142))
18/31 Checking commit 606831a33eda (acpi/pxb/cxl: Reserve host bridge MMIO)
19/31 Checking commit e70de0847b95 (hw/pxb/cxl: Add "windows" for host bridges)
WARNING: line over 80 characters
#133: FILE: hw/pci-bridge/pci_expander_bridge.c:516:
+ warn_report("memory-windows should be set when creating CXL host bridges");
total: 0 errors, 1 warnings, 127 lines checked
Patch 19/31 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
20/31 Checking commit 54b96623ffd8 (hw/cxl/rp: Add a root port)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
total: 0 errors, 1 warnings, 268 lines checked
Patch 20/31 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/31 Checking commit ba804700c6a6 (hw/cxl/device: Add a memory device (8.2.8.5))
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#155:
new file mode 100644
WARNING: line over 80 characters
#272: FILE: hw/mem/cxl_type3.c:113:
+ "Not enough free space (%zd) required for device (%" PRId64 ")",
total: 0 errors, 2 warnings, 501 lines checked
Patch 21/31 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
22/31 Checking commit 7eb80384a516 (hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12))
WARNING: line over 80 characters
#92: FILE: hw/mem/cxl_type3.c:113:
+static void ct3d_reg_write(void *opaque, hwaddr offset, uint64_t value, unsigned size)
total: 0 errors, 1 warnings, 114 lines checked
Patch 22/31 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
23/31 Checking commit 50f82e6dddb1 (acpi/cxl: Add _OSC implementation (9.14.2))
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#45:
new file mode 100644
WARNING: Block comments use a leading /* on a separate line
#188: FILE: hw/i386/acpi-build.c:1210:
+ } else /* CXL */ {
total: 0 errors, 2 warnings, 176 lines checked
Patch 23/31 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
24/31 Checking commit 04a874a8d982 (tests/acpi: allow CEDT table addition)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#16:
new file mode 100644
total: 0 errors, 1 warnings, 3 lines checked
Patch 24/31 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
25/31 Checking commit 6c13c9205746 (acpi/cxl: Create the CEDT (9.14.1))
26/31 Checking commit 43995014aa28 (tests/acpi: Add new CEDT files)
27/31 Checking commit 5f683ab6ee1a (hw/cxl/device: Add some trivial commands)
28/31 Checking commit 8ed7755c7a36 (hw/cxl/device: Plumb real LSA sizing)
29/31 Checking commit c140fd9d4517 (hw/cxl/device: Implement get/set LSA)
30/31 Checking commit 9329c2b72e7f (qtest/cxl: Add very basic sanity tests)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#15:
new file mode 100644
WARNING: line over 80 characters
#36: FILE: tests/qtest/cxl-test.c:17:
+#define QEMU_T3D "-device cxl-type3,bus=rp0,memdev=cxl-mem1,id=cxl-pmem0,size=256M"
total: 0 errors, 2 warnings, 109 lines checked
Patch 30/31 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
31/31 Checking commit e26ed228d062 (WIP: i386/cxl: Initialize a host bridge)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20210202005948.241655-1-ben.widawsky@intel.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
I've started a barebones project plan: https://gitlab.com/bwidawsk/qemu/-/snippets/2070304 Jonathan, if you have a moment, perhaps you can send a MR summarizing CDAT/DOE work from you and Chris? If folks feel priorities are drastically off, we can discuss it in the snippet comments. As for wider acceptance, if I'm looking at this from the QEMU community perspective, better test cases are really needed. If your fingers are itching for some typing, might I suggest starting with that. I've opted not to use issue tracker for this because I am hopeful this won't be a long living gitlab project. On 21-02-01 16:59:17, Ben Widawsky wrote: > Major changes since v2 [1]: > * Removed all register endian/alignment/size checking. Using core functionality > instead. This untested on big endian hosts, but Should Work(tm). > * Fix component capability header generation (off by 1). > * Fixed HDM programming (multiple issues). > * Fixed timestamp command implementations. > * Added commands: GET_FIRMWARE_UPDATE_INFO, GET_PARTITION_INFO, GET_LSA, SET_LSA > > Things have remained fairly stable since since v2. The biggest change here is > definitely the HDM programming which has received limited (but not 0) testing in > the Linux driver. > > Jonathan Cameron has gotten this patch series working on ARM [2], and added some > much sought after functionality [3]. > > --- > > I've started #cxl on OFTC IRC for discussion. Please feel free to use that > channel for questions or suggestions in addition to #qemu. > > --- > > Introduce emulation of Compute Express Link 2.0 > (https://www.computeexpresslink.org/). Specifically, add support for Type 3 > memory expanders with persistent memory. > > The emulation has been critical to get the Linux enabling started [4], it would > be an ideal place to land regression tests for different topology handling, and > there may be applications for this emulation as a way for a guest to manipulate > its address space relative to different performance memories. > > Three of the five CXL component types are emulated with some level of > functionality: host bridge, root port, and memory device. All components and > devices implement basic MMIO. Devices/memory devices implement the mailbo > interface. Basic ACPI support is also included. Upstream ports and downstream > ports aren't implemented (the two components needed to make up a switch). > > CXL 2.0 is built on top of PCIe (see spec for details). As a result, much of the > implementation utilizes existing PCI paradigms. To implement the host bridge, > I've chosen to use PXB (PCI Expander Bridge). It seemed to be the most natural > fit even though it doesn't directly map to how hardware will work. For > persistent capacity of the memory device, I utilized the memory subsystem > (hw/mem). > > We have 3 reasons why this work is valuable: > 1. Linux driver feature development benefits from emulation both due to a lack > of initial hardware availability, but also, as is seen with NVDIMM/PMEM > emulation, there is value in being able to share topologies with > system-software developers even after hardware is available. > > 2. The Linux kernel's unit test suite for NVDIMM/PMEM ended up injecting fake > resources via custom modules (nfit_test). In retrospect a QEMU emulation of > nfit_test capabilities would have made the test environment more portable, > and allowed for easier community contributions of example configurations. > > 3. This is still being fleshed out, but in short it provides a standardized > mechanism for the guest to provide feedback to the host about size and > placement needs of the memory. After the host gives the guest a physical > window mapping to the CXL device, the emulated HDM decoders allow the guest a > way to tell the host how much it wants and where. There are likely simpler > ways to do this, but they'd require inventing a new interface and you'd need > to have diverging driver code in the guest programming of the HDM decoder vs. > the host. Since we've already done this work, why not use it? > > There is quite a long list of work to do for full spec compliance, but I don't > believe that any of it precludes merging. Off the top of my head: > - Main host bridge support (WIP) > - Interleaving > - Better Tests > - Hot plug support > - Emulating volatile capacity > - CDAT emulation [3] > > The flow of the patches in general is to define all the data structures and > registers associated with the various components in a top down manner. Host > bridge, component, ports, devices. Then, the actual implementation is done in > the same order. > > The summary is: > 1-5: Infrastructure for component and device emulation > 6-9: Basic mailbox command implementations > 10-19: Implement CXL host bridges as PXB devices > 20: Implement a root port > 21-22: Implement a memory device > 23-26: ACPI bits > 27-29: Add some more advanced mailbox command implementations > 30: Start working on enabling the main host bridge > 31: Basic test case > > --- > > [1]: https://lore.kernel.org/qemu-devel/20210105165323.783725-1-ben.widawsky@intel.com/ > [2]: https://lore.kernel.org/qemu-devel/20210201152655.31027-1-Jonathan.Cameron@huawei.com/ > [3]: https://lore.kernel.org/qemu-devel/20210201151629.29656-1-Jonathan.Cameron@huawei.com/ > [4]: https://lore.kernel.org/linux-cxl/20210130002438.1872527-1-ben.widawsky@intel.com/ > > --- > > Ben Widawsky (31): > hw/pci/cxl: Add a CXL component type (interface) > hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5) > hw/cxl/device: Introduce a CXL device (8.2.8) > hw/cxl/device: Implement the CAP array (8.2.8.1-2) > hw/cxl/device: Implement basic mailbox (8.2.8.4) > hw/cxl/device: Add memory device utilities > hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1) > hw/cxl/device: Timestamp implementation (8.2.9.3) > hw/cxl/device: Add log commands (8.2.9.4) + CEL > hw/pxb: Use a type for realizing expanders > hw/pci/cxl: Create a CXL bus type > hw/pxb: Allow creation of a CXL PXB (host bridge) > qtest: allow DSDT acpi table changes > acpi/pci: Consolidate host bridge setup > tests/acpi: remove stale allowed tables > hw/pci: Plumb _UID through host bridges > hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) > acpi/pxb/cxl: Reserve host bridge MMIO > hw/pxb/cxl: Add "windows" for host bridges > hw/cxl/rp: Add a root port > hw/cxl/device: Add a memory device (8.2.8.5) > hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) > acpi/cxl: Add _OSC implementation (9.14.2) > tests/acpi: allow CEDT table addition > acpi/cxl: Create the CEDT (9.14.1) > tests/acpi: Add new CEDT files > hw/cxl/device: Add some trivial commands > hw/cxl/device: Plumb real LSA sizing > hw/cxl/device: Implement get/set LSA > qtest/cxl: Add very basic sanity tests > WIP: i386/cxl: Initialize a host bridge > > MAINTAINERS | 6 + > hw/Kconfig | 1 + > hw/acpi/Kconfig | 5 + > hw/acpi/cxl.c | 173 ++++++++++ > hw/acpi/meson.build | 1 + > hw/arm/virt.c | 1 + > hw/core/machine.c | 26 ++ > hw/core/numa.c | 3 + > hw/cxl/Kconfig | 3 + > hw/cxl/cxl-component-utils.c | 208 ++++++++++++ > hw/cxl/cxl-device-utils.c | 264 +++++++++++++++ > hw/cxl/cxl-mailbox-utils.c | 498 ++++++++++++++++++++++++++++ > hw/cxl/meson.build | 5 + > hw/i386/acpi-build.c | 87 ++++- > hw/i386/microvm.c | 1 + > hw/i386/pc.c | 2 + > hw/mem/Kconfig | 5 + > hw/mem/cxl_type3.c | 405 ++++++++++++++++++++++ > hw/mem/meson.build | 1 + > hw/meson.build | 1 + > hw/pci-bridge/Kconfig | 5 + > hw/pci-bridge/cxl_root_port.c | 231 +++++++++++++ > hw/pci-bridge/meson.build | 1 + > hw/pci-bridge/pci_expander_bridge.c | 209 +++++++++++- > hw/pci-bridge/pcie_root_port.c | 6 +- > hw/pci/pci.c | 32 +- > hw/pci/pcie.c | 30 ++ > hw/ppc/spapr.c | 2 + > include/hw/acpi/cxl.h | 27 ++ > include/hw/boards.h | 2 + > include/hw/cxl/cxl.h | 29 ++ > include/hw/cxl/cxl_component.h | 187 +++++++++++ > include/hw/cxl/cxl_device.h | 255 ++++++++++++++ > include/hw/cxl/cxl_pci.h | 160 +++++++++ > include/hw/pci/pci.h | 15 + > include/hw/pci/pci_bridge.h | 25 ++ > include/hw/pci/pci_bus.h | 8 + > include/hw/pci/pci_ids.h | 1 + > monitor/hmp-cmds.c | 15 + > qapi/machine.json | 1 + > tests/data/acpi/pc/CEDT | Bin 0 -> 36 bytes > tests/data/acpi/pc/DSDT | Bin 5065 -> 5065 bytes > tests/data/acpi/pc/DSDT.acpihmat | Bin 6390 -> 6390 bytes > tests/data/acpi/pc/DSDT.bridge | Bin 6924 -> 6924 bytes > tests/data/acpi/pc/DSDT.cphp | Bin 5529 -> 5529 bytes > tests/data/acpi/pc/DSDT.dimmpxm | Bin 6719 -> 6719 bytes > tests/data/acpi/pc/DSDT.hpbridge | Bin 5026 -> 5026 bytes > tests/data/acpi/pc/DSDT.hpbrroot | Bin 3084 -> 3084 bytes > tests/data/acpi/pc/DSDT.ipmikcs | Bin 5137 -> 5137 bytes > tests/data/acpi/pc/DSDT.memhp | Bin 6424 -> 6424 bytes > tests/data/acpi/pc/DSDT.numamem | Bin 5071 -> 5071 bytes > tests/data/acpi/pc/DSDT.roothp | Bin 5261 -> 5261 bytes > tests/data/acpi/q35/CEDT | Bin 0 -> 36 bytes > tests/data/acpi/q35/DSDT | Bin 7801 -> 7801 bytes > tests/data/acpi/q35/DSDT.acpihmat | Bin 9126 -> 9126 bytes > tests/data/acpi/q35/DSDT.bridge | Bin 7819 -> 7819 bytes > tests/data/acpi/q35/DSDT.cphp | Bin 8265 -> 8265 bytes > tests/data/acpi/q35/DSDT.dimmpxm | Bin 9455 -> 9455 bytes > tests/data/acpi/q35/DSDT.ipmibt | Bin 7876 -> 7876 bytes > tests/data/acpi/q35/DSDT.memhp | Bin 9160 -> 9160 bytes > tests/data/acpi/q35/DSDT.mmio64 | Bin 8932 -> 8932 bytes > tests/data/acpi/q35/DSDT.numamem | Bin 7807 -> 7807 bytes > tests/qtest/cxl-test.c | 93 ++++++ > tests/qtest/meson.build | 4 + > 64 files changed, 3004 insertions(+), 30 deletions(-) > create mode 100644 hw/acpi/cxl.c > create mode 100644 hw/cxl/Kconfig > create mode 100644 hw/cxl/cxl-component-utils.c > create mode 100644 hw/cxl/cxl-device-utils.c > create mode 100644 hw/cxl/cxl-mailbox-utils.c > create mode 100644 hw/cxl/meson.build > create mode 100644 hw/mem/cxl_type3.c > create mode 100644 hw/pci-bridge/cxl_root_port.c > create mode 100644 include/hw/acpi/cxl.h > create mode 100644 include/hw/cxl/cxl.h > create mode 100644 include/hw/cxl/cxl_component.h > create mode 100644 include/hw/cxl/cxl_device.h > create mode 100644 include/hw/cxl/cxl_pci.h > create mode 100644 tests/data/acpi/pc/CEDT > create mode 100644 tests/data/acpi/q35/CEDT > create mode 100644 tests/qtest/cxl-test.c > > -- > 2.30.0 > >
On Wed, 3 Feb 2021 09:42:16 -0800 Ben Widawsky <ben@bwidawsk.net> wrote: > I've started a barebones project plan: > https://gitlab.com/bwidawsk/qemu/-/snippets/2070304 Great. > > Jonathan, if you have a moment, perhaps you can send a MR summarizing CDAT/DOE > work from you and Chris? I need to catch up with what Chris has posted, but sure after that I'll add to your doc if Chris doesn't get there first. My intent is to let Chris get on with the DOE QEMU support. Plenty of other stuff to do as long as it covers what I need (if not I'll hack stuff on top :) Will catch up with reviewing that in the next few days. I'll also add some other comments on the plan when I get a chance. Will need to fake at least a partial switch sometime soon for example. > > If folks feel priorities are drastically off, we can discuss it in the snippet > comments. > > As for wider acceptance, if I'm looking at this from the QEMU community > perspective, better test cases are really needed. If your fingers are itching > for some typing, might I suggest starting with that. > > I've opted not to use issue tracker for this because I am hopeful this won't be > a long living gitlab project. All sounds good. I've not reviewed that much on the last few patches in here, at least partly because a bunch of them have todo comments so I'm assuming they are very much a work in progress. One thing I will note is this has become large and complex enough that I'd be tempted to start separating the 'racey cutting edge' parts from bits that have been moderately stable for a while. Hopefully some of that stable part can get wider review without the fun stuff and all the churn related to that. Jonathan > > On 21-02-01 16:59:17, Ben Widawsky wrote: > > Major changes since v2 [1]: > > * Removed all register endian/alignment/size checking. Using core functionality > > instead. This untested on big endian hosts, but Should Work(tm). > > * Fix component capability header generation (off by 1). > > * Fixed HDM programming (multiple issues). > > * Fixed timestamp command implementations. > > * Added commands: GET_FIRMWARE_UPDATE_INFO, GET_PARTITION_INFO, GET_LSA, SET_LSA > > > > Things have remained fairly stable since since v2. The biggest change here is > > definitely the HDM programming which has received limited (but not 0) testing in > > the Linux driver. > > > > Jonathan Cameron has gotten this patch series working on ARM [2], and added some > > much sought after functionality [3]. > > > > --- > > > > I've started #cxl on OFTC IRC for discussion. Please feel free to use that > > channel for questions or suggestions in addition to #qemu. > > > > --- > > > > Introduce emulation of Compute Express Link 2.0 > > (https://www.computeexpresslink.org/). Specifically, add support for Type 3 > > memory expanders with persistent memory. > > > > The emulation has been critical to get the Linux enabling started [4], it would > > be an ideal place to land regression tests for different topology handling, and > > there may be applications for this emulation as a way for a guest to manipulate > > its address space relative to different performance memories. > > > > Three of the five CXL component types are emulated with some level of > > functionality: host bridge, root port, and memory device. All components and > > devices implement basic MMIO. Devices/memory devices implement the mailbo > > interface. Basic ACPI support is also included. Upstream ports and downstream > > ports aren't implemented (the two components needed to make up a switch). > > > > CXL 2.0 is built on top of PCIe (see spec for details). As a result, much of the > > implementation utilizes existing PCI paradigms. To implement the host bridge, > > I've chosen to use PXB (PCI Expander Bridge). It seemed to be the most natural > > fit even though it doesn't directly map to how hardware will work. For > > persistent capacity of the memory device, I utilized the memory subsystem > > (hw/mem). > > > > We have 3 reasons why this work is valuable: > > 1. Linux driver feature development benefits from emulation both due to a lack > > of initial hardware availability, but also, as is seen with NVDIMM/PMEM > > emulation, there is value in being able to share topologies with > > system-software developers even after hardware is available. > > > > 2. The Linux kernel's unit test suite for NVDIMM/PMEM ended up injecting fake > > resources via custom modules (nfit_test). In retrospect a QEMU emulation of > > nfit_test capabilities would have made the test environment more portable, > > and allowed for easier community contributions of example configurations. > > > > 3. This is still being fleshed out, but in short it provides a standardized > > mechanism for the guest to provide feedback to the host about size and > > placement needs of the memory. After the host gives the guest a physical > > window mapping to the CXL device, the emulated HDM decoders allow the guest a > > way to tell the host how much it wants and where. There are likely simpler > > ways to do this, but they'd require inventing a new interface and you'd need > > to have diverging driver code in the guest programming of the HDM decoder vs. > > the host. Since we've already done this work, why not use it? > > > > There is quite a long list of work to do for full spec compliance, but I don't > > believe that any of it precludes merging. Off the top of my head: > > - Main host bridge support (WIP) > > - Interleaving > > - Better Tests > > - Hot plug support > > - Emulating volatile capacity > > - CDAT emulation [3] > > > > The flow of the patches in general is to define all the data structures and > > registers associated with the various components in a top down manner. Host > > bridge, component, ports, devices. Then, the actual implementation is done in > > the same order. > > > > The summary is: > > 1-5: Infrastructure for component and device emulation > > 6-9: Basic mailbox command implementations > > 10-19: Implement CXL host bridges as PXB devices > > 20: Implement a root port > > 21-22: Implement a memory device > > 23-26: ACPI bits > > 27-29: Add some more advanced mailbox command implementations > > 30: Start working on enabling the main host bridge > > 31: Basic test case > > > > --- > > > > [1]: https://lore.kernel.org/qemu-devel/20210105165323.783725-1-ben.widawsky@intel.com/ > > [2]: https://lore.kernel.org/qemu-devel/20210201152655.31027-1-Jonathan.Cameron@huawei.com/ > > [3]: https://lore.kernel.org/qemu-devel/20210201151629.29656-1-Jonathan.Cameron@huawei.com/ > > [4]: https://lore.kernel.org/linux-cxl/20210130002438.1872527-1-ben.widawsky@intel.com/ > > > > --- > > > > Ben Widawsky (31): > > hw/pci/cxl: Add a CXL component type (interface) > > hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5) > > hw/cxl/device: Introduce a CXL device (8.2.8) > > hw/cxl/device: Implement the CAP array (8.2.8.1-2) > > hw/cxl/device: Implement basic mailbox (8.2.8.4) > > hw/cxl/device: Add memory device utilities > > hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1) > > hw/cxl/device: Timestamp implementation (8.2.9.3) > > hw/cxl/device: Add log commands (8.2.9.4) + CEL > > hw/pxb: Use a type for realizing expanders > > hw/pci/cxl: Create a CXL bus type > > hw/pxb: Allow creation of a CXL PXB (host bridge) > > qtest: allow DSDT acpi table changes > > acpi/pci: Consolidate host bridge setup > > tests/acpi: remove stale allowed tables > > hw/pci: Plumb _UID through host bridges > > hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) > > acpi/pxb/cxl: Reserve host bridge MMIO > > hw/pxb/cxl: Add "windows" for host bridges > > hw/cxl/rp: Add a root port > > hw/cxl/device: Add a memory device (8.2.8.5) > > hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) > > acpi/cxl: Add _OSC implementation (9.14.2) > > tests/acpi: allow CEDT table addition > > acpi/cxl: Create the CEDT (9.14.1) > > tests/acpi: Add new CEDT files > > hw/cxl/device: Add some trivial commands > > hw/cxl/device: Plumb real LSA sizing > > hw/cxl/device: Implement get/set LSA > > qtest/cxl: Add very basic sanity tests > > WIP: i386/cxl: Initialize a host bridge > > > > MAINTAINERS | 6 + > > hw/Kconfig | 1 + > > hw/acpi/Kconfig | 5 + > > hw/acpi/cxl.c | 173 ++++++++++ > > hw/acpi/meson.build | 1 + > > hw/arm/virt.c | 1 + > > hw/core/machine.c | 26 ++ > > hw/core/numa.c | 3 + > > hw/cxl/Kconfig | 3 + > > hw/cxl/cxl-component-utils.c | 208 ++++++++++++ > > hw/cxl/cxl-device-utils.c | 264 +++++++++++++++ > > hw/cxl/cxl-mailbox-utils.c | 498 ++++++++++++++++++++++++++++ > > hw/cxl/meson.build | 5 + > > hw/i386/acpi-build.c | 87 ++++- > > hw/i386/microvm.c | 1 + > > hw/i386/pc.c | 2 + > > hw/mem/Kconfig | 5 + > > hw/mem/cxl_type3.c | 405 ++++++++++++++++++++++ > > hw/mem/meson.build | 1 + > > hw/meson.build | 1 + > > hw/pci-bridge/Kconfig | 5 + > > hw/pci-bridge/cxl_root_port.c | 231 +++++++++++++ > > hw/pci-bridge/meson.build | 1 + > > hw/pci-bridge/pci_expander_bridge.c | 209 +++++++++++- > > hw/pci-bridge/pcie_root_port.c | 6 +- > > hw/pci/pci.c | 32 +- > > hw/pci/pcie.c | 30 ++ > > hw/ppc/spapr.c | 2 + > > include/hw/acpi/cxl.h | 27 ++ > > include/hw/boards.h | 2 + > > include/hw/cxl/cxl.h | 29 ++ > > include/hw/cxl/cxl_component.h | 187 +++++++++++ > > include/hw/cxl/cxl_device.h | 255 ++++++++++++++ > > include/hw/cxl/cxl_pci.h | 160 +++++++++ > > include/hw/pci/pci.h | 15 + > > include/hw/pci/pci_bridge.h | 25 ++ > > include/hw/pci/pci_bus.h | 8 + > > include/hw/pci/pci_ids.h | 1 + > > monitor/hmp-cmds.c | 15 + > > qapi/machine.json | 1 + > > tests/data/acpi/pc/CEDT | Bin 0 -> 36 bytes > > tests/data/acpi/pc/DSDT | Bin 5065 -> 5065 bytes > > tests/data/acpi/pc/DSDT.acpihmat | Bin 6390 -> 6390 bytes > > tests/data/acpi/pc/DSDT.bridge | Bin 6924 -> 6924 bytes > > tests/data/acpi/pc/DSDT.cphp | Bin 5529 -> 5529 bytes > > tests/data/acpi/pc/DSDT.dimmpxm | Bin 6719 -> 6719 bytes > > tests/data/acpi/pc/DSDT.hpbridge | Bin 5026 -> 5026 bytes > > tests/data/acpi/pc/DSDT.hpbrroot | Bin 3084 -> 3084 bytes > > tests/data/acpi/pc/DSDT.ipmikcs | Bin 5137 -> 5137 bytes > > tests/data/acpi/pc/DSDT.memhp | Bin 6424 -> 6424 bytes > > tests/data/acpi/pc/DSDT.numamem | Bin 5071 -> 5071 bytes > > tests/data/acpi/pc/DSDT.roothp | Bin 5261 -> 5261 bytes > > tests/data/acpi/q35/CEDT | Bin 0 -> 36 bytes > > tests/data/acpi/q35/DSDT | Bin 7801 -> 7801 bytes > > tests/data/acpi/q35/DSDT.acpihmat | Bin 9126 -> 9126 bytes > > tests/data/acpi/q35/DSDT.bridge | Bin 7819 -> 7819 bytes > > tests/data/acpi/q35/DSDT.cphp | Bin 8265 -> 8265 bytes > > tests/data/acpi/q35/DSDT.dimmpxm | Bin 9455 -> 9455 bytes > > tests/data/acpi/q35/DSDT.ipmibt | Bin 7876 -> 7876 bytes > > tests/data/acpi/q35/DSDT.memhp | Bin 9160 -> 9160 bytes > > tests/data/acpi/q35/DSDT.mmio64 | Bin 8932 -> 8932 bytes > > tests/data/acpi/q35/DSDT.numamem | Bin 7807 -> 7807 bytes > > tests/qtest/cxl-test.c | 93 ++++++ > > tests/qtest/meson.build | 4 + > > 64 files changed, 3004 insertions(+), 30 deletions(-) > > create mode 100644 hw/acpi/cxl.c > > create mode 100644 hw/cxl/Kconfig > > create mode 100644 hw/cxl/cxl-component-utils.c > > create mode 100644 hw/cxl/cxl-device-utils.c > > create mode 100644 hw/cxl/cxl-mailbox-utils.c > > create mode 100644 hw/cxl/meson.build > > create mode 100644 hw/mem/cxl_type3.c > > create mode 100644 hw/pci-bridge/cxl_root_port.c > > create mode 100644 include/hw/acpi/cxl.h > > create mode 100644 include/hw/cxl/cxl.h > > create mode 100644 include/hw/cxl/cxl_component.h > > create mode 100644 include/hw/cxl/cxl_device.h > > create mode 100644 include/hw/cxl/cxl_pci.h > > create mode 100644 tests/data/acpi/pc/CEDT > > create mode 100644 tests/data/acpi/q35/CEDT > > create mode 100644 tests/qtest/cxl-test.c > > > > -- > > 2.30.0 > > > >