| Message ID | 1617766086-5502-6-git-send-email-flora.fu@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Support for MediaTek MT8192 APU Power | expand |
On Wed, 07 Apr 2021 11:28:03 +0800, Flora Fu wrote: > Document the bindings for APU power domain on MediaTek SoC. > > Signed-off-by: Flora Fu <flora.fu@mediatek.com> > --- > .../soc/mediatek/mediatek,apu-pm.yaml | 146 ++++++++++++++++++ > 1 file changed, 146 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.example.dts:19:18: fatal error: dt-bindings/clock/mt8192-clk.h: No such file or directory 19 | #include <dt-bindings/clock/mt8192-clk.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[1]: *** [scripts/Makefile.lib:377: Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.example.dt.yaml] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1414: dt_binding_check] Error 2 See https://patchwork.ozlabs.org/patch/1463115 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
Hi, Rob, The error is resulted from some un-merged patch. Please note that the patch depends MT8192 clock patches which haven't yet been accepted. https://patchwork.kernel.org/project/linux-mediatek/patch/20210324104110.13383-7-chun-jie.chen@mediatek.com/ Thanks for your review. On Wed, 2021-04-07 at 09:28 -0500, Rob Herring wrote: > On Wed, 07 Apr 2021 11:28:03 +0800, Flora Fu wrote: > > Document the bindings for APU power domain on MediaTek SoC. > > > > Signed-off-by: Flora Fu <flora.fu@mediatek.com> > > --- > > .../soc/mediatek/mediatek,apu-pm.yaml | 146 ++++++++++++++++++ > > 1 file changed, 146 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.example.dts:19:18: fatal error: dt-bindings/clock/mt8192-clk.h: No such file or directory > 19 | #include <dt-bindings/clock/mt8192-clk.h> > | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > compilation terminated. > make[1]: *** [scripts/Makefile.lib:377: Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.example.dt.yaml] Error 1 > make[1]: *** Waiting for unfinished jobs.... > make: *** [Makefile:1414: dt_binding_check] Error 2 > > See https://urldefense.com/v3/__https://patchwork.ozlabs.org/patch/1463115__;!!CTRNKA9wMg0ARbw!0XUn1LcNHfvUShNClpM_yH73TAR9qdm29SZMckasoCQ8UzeKS-vZW0QUu3Ssn-s6$ > > This check can fail if there are any dependencies. The base for a patch > series is generally the most recent rc1. > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit. >
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml new file mode 100644 index 000000000000..c99e812977f9 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,apu-pm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek APU Power Domains + +maintainers: + - Flora Fu <flora.fu@mediatek.com> + +description: | + Mediatek AI Process Unit (APU) include support for power domains which can be + powered up/down by software. + APU subsys belonging to a power domain should contain a 'power-domains' + property that is a phandle for apuspm node representing the domain. + +properties: + compatible: + items: + - enum: + - mediatek,mt8192-apu-pm + - const: syscon + + reg: + description: Address range of the APU power domain controller. + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + '#power-domain-cells': + const: 1 + + vsram-supply: + description: apu sram regulator supply. + + mediatek,scpsys: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + phandle to the device containing the scpsys register range. + + mediatek,apu_conn: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + phandle to the device containing the scpsys apu conn register range. + + mediatek,apu_conn1: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + phandle to the device containing the scpsys apu conn1 register range. + + mediatek,apu_vcore: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + phandle to the device containing the scpsys apu vcore register range. + +patternProperties: + "^power-domain@[0-9a-f]+$": + type: object + description: | + Represents the power domains within the power controller node as + documented in Documentation/devicetree/bindings/power/power-domain.yaml. + + properties: + reg: + description: | + Power domain index. Valid values are defined in: + "include/dt-bindings/power/mt8182-apu-power.h" + maxItems: 1 + + '#power-domain-cells': + description: | + Must be 0 for nodes representing a single PM domain and 1 for nodes + providing multiple PM. + + clocks: + description: | + List of phandles of clocks list. Specify by order according to + power-up sequence. + + clock-names: + description: | + List of names of clocks. Specify by order according to power-up + sequence. + + assigned-clocks: + maxItems: 2 + + assigned-clock-parents: + maxItems: 2 + + domain-supply: + description: domain regulator supply. + + required: + - reg + - '#power-domain-cells' + + additionalProperties: false + +required: + - compatible + - reg + - '#power-domain-cells' + - vsram-supply + - mediatek,scpsys + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8192-clk.h> + #include <dt-bindings/power/mt8192-apu-power.h> + apuspm: power-domain@190f0000 { + compatible = "mediatek,mt8192-apu-pm", "syscon"; + reg = <0x190f0000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + vsram-supply = <&mt6359_vsram_md_ldo_reg>; + mediatek,scpsys = <&scpsys>; + mediatek,apu_conn = <&apu_conn>; + mediatek,apu_vcore = <&apu_vcore>; + + power-domain@MT8192_POWER_DOMAIN_APUSYS_TOP { + reg = <MT8192_POWER_DOMAIN_APUSYS_TOP>; + #power-domain-cells = <0>; + clocks = <&topckgen CLK_TOP_DSP_SEL>, + <&topckgen CLK_TOP_IPU_IF_SEL>, + <&clk26m>, + <&topckgen CLK_TOP_UNIVPLL_D6_D2>; + clock-names = "clk_top_conn", + "clk_top_ipu_if", + "clk_off", + "clk_on_default"; + assigned-clocks = <&topckgen CLK_TOP_DSP_SEL>, + <&topckgen CLK_TOP_IPU_IF_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_UNIVPLL_D6_D2>; + domain-supply = <&mt6359_vproc1_buck_reg>; + }; + };
Document the bindings for APU power domain on MediaTek SoC. Signed-off-by: Flora Fu <flora.fu@mediatek.com> --- .../soc/mediatek/mediatek,apu-pm.yaml | 146 ++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml