| Message ID | 2f896dc4e83197f4fe40c08c45e38bbdcc5c0dbe.1617804573.git.viremana@linux.microsoft.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Hyper-V nested virt enlightenments for SVM | expand |
From: Vineeth Pillai <viremana@linux.microsoft.com> Sent: Wednesday, April 7, 2021 7:41 AM > > Bit 22 of HYPERV_CPUID_FEATURES.EDX is specific to SVM and specifies > support for enlightened TLB flush. With this enligtenment enabled, s/enligtenment/enlightenment/ > ASID invalidations flushes only gva->hpa entries. To flush TLB entries > derived from NPT, hypercalls should be used > (HvFlushGuestPhysicalAddressSpace or HvFlushGuestPhysicalAddressList) > > Signed-off-by: Vineeth Pillai <viremana@linux.microsoft.com> > --- > arch/x86/include/asm/hyperv-tlfs.h | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/x86/include/asm/hyperv-tlfs.h b/arch/x86/include/asm/hyperv-tlfs.h > index 606f5cc579b2..005bf14d0449 100644 > --- a/arch/x86/include/asm/hyperv-tlfs.h > +++ b/arch/x86/include/asm/hyperv-tlfs.h > @@ -133,6 +133,15 @@ > #define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18) > #define HV_X64_NESTED_MSR_BITMAP BIT(19) > > +/* > + * This is specific to AMD and specifies that enlightened TLB flush is > + * supported. If guest opts in to this feature, ASID invalidations only > + * flushes gva -> hpa mapping entries. To flush the TLB entries derived > + * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace > + * or HvFlushGuestPhysicalAddressList). > + */ > +#define HV_X64_NESTED_ENLIGHTENED_TLB BIT(22) > + > /* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */ > #define HV_PARAVISOR_PRESENT BIT(0) > > -- > 2.25.1
On 4/7/21 3:56 PM, Michael Kelley wrote: > From: Vineeth Pillai <viremana@linux.microsoft.com> Sent: Wednesday, April 7, 2021 7:41 AM >> Bit 22 of HYPERV_CPUID_FEATURES.EDX is specific to SVM and specifies >> support for enlightened TLB flush. With this enligtenment enabled, > s/enligtenment/enlightenment/ Thanks for catching this, will fix. Thanks, Vineeth
diff --git a/arch/x86/include/asm/hyperv-tlfs.h b/arch/x86/include/asm/hyperv-tlfs.h index 606f5cc579b2..005bf14d0449 100644 --- a/arch/x86/include/asm/hyperv-tlfs.h +++ b/arch/x86/include/asm/hyperv-tlfs.h @@ -133,6 +133,15 @@ #define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18) #define HV_X64_NESTED_MSR_BITMAP BIT(19) +/* + * This is specific to AMD and specifies that enlightened TLB flush is + * supported. If guest opts in to this feature, ASID invalidations only + * flushes gva -> hpa mapping entries. To flush the TLB entries derived + * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace + * or HvFlushGuestPhysicalAddressList). + */ +#define HV_X64_NESTED_ENLIGHTENED_TLB BIT(22) + /* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */ #define HV_PARAVISOR_PRESENT BIT(0)
Bit 22 of HYPERV_CPUID_FEATURES.EDX is specific to SVM and specifies support for enlightened TLB flush. With this enligtenment enabled, ASID invalidations flushes only gva->hpa entries. To flush TLB entries derived from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace or HvFlushGuestPhysicalAddressList) Signed-off-by: Vineeth Pillai <viremana@linux.microsoft.com> --- arch/x86/include/asm/hyperv-tlfs.h | 9 +++++++++ 1 file changed, 9 insertions(+)