| Message ID | 20210406045041.16283-2-ansuelsmth@gmail.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | [v2,1/2] include: net: add dsa_cpu_ports function | expand |
| Context | Check | Description |
|---|---|---|
| netdev/cover_letter | success | Link |
| netdev/fixes_present | success | Link |
| netdev/patch_count | success | Link |
| netdev/tree_selection | success | Guessed tree name to be net-next |
| netdev/subject_prefix | warning | Target tree name not specified in the subject |
| netdev/cc_maintainers | success | CCed 7 of 7 maintainers |
| netdev/source_inline | success | Was 0 now: 0 |
| netdev/verify_signedoff | success | Link |
| netdev/module_param | success | Was 0 now: 0 |
| netdev/build_32bit | success | Errors and warnings before: 0 this patch: 0 |
| netdev/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| netdev/verify_fixes | success | Link |
| netdev/checkpatch | warning | WARNING: line length of 89 exceeds 80 columns WARNING: line length of 93 exceeds 80 columns |
| netdev/build_allmodconfig_warn | success | Errors and warnings before: 0 this patch: 0 |
| netdev/header_inline | success | Link |
On Wed, Apr 07, 2021 at 02:41:02AM +0200, Andrew Lunn wrote: > On Tue, Apr 06, 2021 at 06:50:40AM +0200, Ansuel Smith wrote: > > qca8k 83xx switch have 2 cpu ports. Rework the driver to support > > multiple cpu port. All ports can access both cpu ports by default as > > they support the same features. > > Do you have more information about how this actually works. How does > the switch decide which port to use when sending a frame towards the > CPU? Is there some sort of load balancing? > > How does Linux decide which CPU port to use towards the switch? > > Andrew I could be very wrong, but in the current dsa code, only the very first cpu port is used and linux use only that to send data. In theory the switch send the frame to both CPU, I'm currently testing a multi-cpu patch for dsa and I can confirm that with the proposed code the packets are transmitted correctly and the 2 cpu ports are used. (The original code has one cpu dedicated to LAN ports and one cpu dedicated to the unique WAN port.) Anyway in the current implementation nothing will change. DSA code still supports one cpu and this change would only allow packet to be received and trasmitted from the second cpu.
On Tue, Apr 06, 2021 at 06:50:40AM +0200, Ansuel Smith wrote: > qca8k 83xx switch have 2 cpu ports. Rework the driver to support > multiple cpu port. All ports can access both cpu ports by default as > they support the same features. Do you have more information about how this actually works. How does the switch decide which port to use when sending a frame towards the CPU? Is there some sort of load balancing? How does Linux decide which CPU port to use towards the switch? Andrew
On Fri, Apr 09, 2021 at 11:15:37AM -0700, Florian Fainelli wrote: > > > On 4/5/2021 10:16 PM, Ansuel Smith wrote: > > On Wed, Apr 07, 2021 at 02:41:02AM +0200, Andrew Lunn wrote: > >> On Tue, Apr 06, 2021 at 06:50:40AM +0200, Ansuel Smith wrote: > >>> qca8k 83xx switch have 2 cpu ports. Rework the driver to support > >>> multiple cpu port. All ports can access both cpu ports by default as > >>> they support the same features. > >> > >> Do you have more information about how this actually works. How does > >> the switch decide which port to use when sending a frame towards the > >> CPU? Is there some sort of load balancing? > >> > >> How does Linux decide which CPU port to use towards the switch? > >> > >> Andrew > > > > I could be very wrong, but in the current dsa code, only the very first > > cpu port is used and linux use only that to send data. > > That is correct, the first CPU port that is detected by the parsing > logic gets used. > > > In theory the switch send the frame to both CPU, I'm currently testing a > > multi-cpu patch for dsa and I can confirm that with the proposed code > > the packets are transmitted correctly and the 2 cpu ports are used. > > (The original code has one cpu dedicated to LAN ports and one cpu > > dedicated to the unique WAN port.) Anyway in the current implementation > > nothing will change. DSA code still supports one cpu and this change > > would only allow packet to be received and trasmitted from the second > > cpu. > > That use case seems to be the most common which makes sense since it > allows for true Gigabit routing between WAN and LAN by utilizing both > CPUs's Ethernet controllers. > > How do you currently assign a port of a switch with a particular CPU > port this is presumably done through a separate patch that you have not > submitted? > -- > Florian I reworked an old patch that added multi-cpu support to dsa. CPUs are assigned in a round-robin way and they can be set with an additional iproute command. (I read some of the comments in that RFC series and I'm planning to introduce some type of function where the switch driver can declare a preferred CPU port). Anyway this series is just to try to upstream the changes that doesn't require major revision, since they can be included even without the multi-cpu patch.
On 4/5/2021 10:16 PM, Ansuel Smith wrote: > On Wed, Apr 07, 2021 at 02:41:02AM +0200, Andrew Lunn wrote: >> On Tue, Apr 06, 2021 at 06:50:40AM +0200, Ansuel Smith wrote: >>> qca8k 83xx switch have 2 cpu ports. Rework the driver to support >>> multiple cpu port. All ports can access both cpu ports by default as >>> they support the same features. >> >> Do you have more information about how this actually works. How does >> the switch decide which port to use when sending a frame towards the >> CPU? Is there some sort of load balancing? >> >> How does Linux decide which CPU port to use towards the switch? >> >> Andrew > > I could be very wrong, but in the current dsa code, only the very first > cpu port is used and linux use only that to send data. That is correct, the first CPU port that is detected by the parsing logic gets used. > In theory the switch send the frame to both CPU, I'm currently testing a > multi-cpu patch for dsa and I can confirm that with the proposed code > the packets are transmitted correctly and the 2 cpu ports are used. > (The original code has one cpu dedicated to LAN ports and one cpu > dedicated to the unique WAN port.) Anyway in the current implementation > nothing will change. DSA code still supports one cpu and this change > would only allow packet to be received and trasmitted from the second > cpu. That use case seems to be the most common which makes sense since it allows for true Gigabit routing between WAN and LAN by utilizing both CPUs's Ethernet controllers. How do you currently assign a port of a switch with a particular CPU port this is presumably done through a separate patch that you have not submitted?
diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index cdaf9f85a2cb..942d2a75f709 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -724,11 +724,6 @@ qca8k_setup(struct dsa_switch *ds) /* Enable MIB counters */ qca8k_mib_init(priv); - /* Enable QCA header mode on the cpu port */ - qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT), - QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S | - QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S); - /* Disable forwarding by default on all ports */ for (i = 0; i < QCA8K_NUM_PORTS; i++) qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), @@ -749,7 +744,12 @@ qca8k_setup(struct dsa_switch *ds) for (i = 0; i < QCA8K_NUM_PORTS; i++) { /* CPU port gets connected to all user ports of the switch */ if (dsa_is_cpu_port(ds, i)) { - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT), + /* Enable QCA header mode on the cpu port */ + qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(i), + QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S | + QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S); + + qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds)); } @@ -759,7 +759,7 @@ qca8k_setup(struct dsa_switch *ds) qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), QCA8K_PORT_LOOKUP_MEMBER, - BIT(QCA8K_CPU_PORT)); + dsa_cpu_ports(ds)); /* Enable ARP Auto-learning by default */ qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i), @@ -1140,7 +1140,7 @@ static int qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br) { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - int port_mask = BIT(QCA8K_CPU_PORT); + int port_mask = dsa_cpu_ports(ds); int i; for (i = 1; i < QCA8K_NUM_PORTS; i++) { @@ -1183,7 +1183,7 @@ qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br) * this port */ qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_MEMBER, BIT(QCA8K_CPU_PORT)); + QCA8K_PORT_LOOKUP_MEMBER, dsa_cpu_ports(ds)); } static int diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 7ca4b93e0bb5..17bc643231c3 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -20,8 +20,6 @@ #define QCA8K_NUM_FDB_RECORDS 2048 -#define QCA8K_CPU_PORT 0 - #define QCA8K_PORT_VID_DEF 1 /* Global control registers */
qca8k 83xx switch have 2 cpu ports. Rework the driver to support multiple cpu port. All ports can access both cpu ports by default as they support the same features. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> --- drivers/net/dsa/qca8k.c | 18 +++++++++--------- drivers/net/dsa/qca8k.h | 2 -- 2 files changed, 9 insertions(+), 11 deletions(-)