| Message ID | 20210430115355.30611-1-anshuman.gupta@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [RFC,v2] drm/i915: lpsp with hdmi/dp outputs | expand |
On Fri, Apr 30, 2021 at 05:23:55PM +0530, Anshuman Gupta wrote: > DG1 and DISPLAY_VER=13 onwards Audio MMIO/VERBS lies in PG0 power > well. So in order to detect audio capable DP/HDMI output it doesn't > require to enable PG3 power well on DG1 and PG2 on DISPLAY_VER=13 > pltform. It will save the power when DP/HDMI outputs used as > lpsp configuration. > > B.Spec: 49233 > B.Spec: 49231 > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Kai Vehmanen <kai.vehmanen@linux.intel.com> > Cc: Uma Shankar <uma.shankar@intel.com> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 6280ba7f4c17..16bfa7628970 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -3536,8 +3536,13 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state) > mask |= BIT_ULL(intel_encoder->power_domain); > } > > - if (HAS_DDI(dev_priv) && crtc_state->has_audio) > - mask |= BIT_ULL(POWER_DOMAIN_AUDIO); > + if (HAS_DDI(dev_priv) && crtc_state->has_audio) { > + /* if Audio mmio/verbs lies in PG0 */ > + if (IS_DG1(dev_priv) || DISPLAY_VER(dev_priv) >= 11) > + mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE); > + else > + mask |= BIT_ULL(POWER_DOMAIN_AUDIO); Power domains are supposed to be abstract. So if the audio stuff is moving to a different power well then we just need to adjust the domain for the relevant power wells. > + } > > if (crtc_state->shared_dpll) > mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE); > -- > 2.26.2
> -----Original Message----- > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > Sent: Friday, April 30, 2021 11:10 PM > To: Gupta, Anshuman <anshuman.gupta@intel.com> > Cc: intel-gfx@lists.freedesktop.org; Kai Vehmanen > <kai.vehmanen@linux.intel.com>; Shankar, Uma <uma.shankar@intel.com> > Subject: Re: [RFC v2] drm/i915: lpsp with hdmi/dp outputs > > On Fri, Apr 30, 2021 at 05:23:55PM +0530, Anshuman Gupta wrote: > > DG1 and DISPLAY_VER=13 onwards Audio MMIO/VERBS lies in PG0 power > > well. So in order to detect audio capable DP/HDMI output it doesn't > > require to enable PG3 power well on DG1 and PG2 on DISPLAY_VER=13 > > pltform. It will save the power when DP/HDMI outputs used as lpsp > > configuration. > > > > B.Spec: 49233 > > B.Spec: 49231 > > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Cc: Kai Vehmanen <kai.vehmanen@linux.intel.com> > > Cc: Uma Shankar <uma.shankar@intel.com> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++-- > > 1 file changed, 7 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > > b/drivers/gpu/drm/i915/display/intel_display.c > > index 6280ba7f4c17..16bfa7628970 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -3536,8 +3536,13 @@ static u64 get_crtc_power_domains(struct > intel_crtc_state *crtc_state) > > mask |= BIT_ULL(intel_encoder->power_domain); > > } > > > > - if (HAS_DDI(dev_priv) && crtc_state->has_audio) > > - mask |= BIT_ULL(POWER_DOMAIN_AUDIO); > > + if (HAS_DDI(dev_priv) && crtc_state->has_audio) { > > + /* if Audio mmio/verbs lies in PG0 */ > > + if (IS_DG1(dev_priv) || DISPLAY_VER(dev_priv) >= 11) > > + mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE); > > + else > > + mask |= BIT_ULL(POWER_DOMAIN_AUDIO); > > Power domains are supposed to be abstract. So if the audio stuff is moving to a > different power well then we just need to adjust the domain for the relevant > power wells. Currently we have same power well for DG1 and TGL, this particular delta has been introduced from DG1 onwards and this delta is present for DISPLAY_VER 13 as well. So in order to adjust this delta for DG1 , we will require a separate power well meta data for DG1. @imre could you please provide your input to handle above delta on DG1. How about breaking down POWER_DOMAIN_AUDIO to POWER_DOMAIN_AUDIO_VERBS and POWER_DOMAIN_AUDIO_PLAYBACK? Thanks, Anshuman Gupta. > > > + } > > > > if (crtc_state->shared_dpll) > > mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE); > > -- > > 2.26.2 > > -- > Ville Syrjälä > Intel
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 6280ba7f4c17..16bfa7628970 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3536,8 +3536,13 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state) mask |= BIT_ULL(intel_encoder->power_domain); } - if (HAS_DDI(dev_priv) && crtc_state->has_audio) - mask |= BIT_ULL(POWER_DOMAIN_AUDIO); + if (HAS_DDI(dev_priv) && crtc_state->has_audio) { + /* if Audio mmio/verbs lies in PG0 */ + if (IS_DG1(dev_priv) || DISPLAY_VER(dev_priv) >= 11) + mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE); + else + mask |= BIT_ULL(POWER_DOMAIN_AUDIO); + } if (crtc_state->shared_dpll) mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
DG1 and DISPLAY_VER=13 onwards Audio MMIO/VERBS lies in PG0 power well. So in order to detect audio capable DP/HDMI output it doesn't require to enable PG3 power well on DG1 and PG2 on DISPLAY_VER=13 pltform. It will save the power when DP/HDMI outputs used as lpsp configuration. B.Spec: 49233 B.Spec: 49231 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Kai Vehmanen <kai.vehmanen@linux.intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)