| Message ID | 75a66bae21937da1c69e8024ce61b35aad4ac9b8.1620119570.git.geert+renesas@glider.be (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 8d65807654570ed757fd00bde72fe81901101e2f |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | arm64: dts: renesas: eagle: Add x1 clock | expand |
Hi Geert, Valentine, On 04/05/2021 10:14, Geert Uytterhoeven wrote: > From: Valentine Barshak <valentine.barshak@cogentembedded.com> > > This adds X1 clock which supplies a frequency of 148.5 MHz. > This clock is connected to the external dot clock input signal. > > Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> > [geert: Verified schematics] > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > Untested due to lack of hardware Tested on my Eagle-V3M with running the DU tests: Testing composition on CRTC 46: SUCCESS Testing connector HDMI-A-1: SUCCESS Testing plane formats: SUCCESS Testing legacy mode set on connector HDMI-A-1: SUCCESS Testing modes on connector HDMI-A-1: SUCCESS Testing atomic mode set on connector HDMI-A-1: SUCCESS Testing page flip on connector HDMI-A-1: SUCCESS Testing plane positioning boundaries: SUCCESS and verifying that the output visible was as expected. Tested-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> > --- > arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts > index 874a7fc2730b00db..5c84681703edad2e 100644 > --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts > +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts > @@ -73,6 +73,12 @@ memory@48000000 { > /* first 128MB is reserved for secure area. */ > reg = <0x0 0x48000000 0x0 0x38000000>; > }; > + > + x1_clk: x1-clock { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <148500000>; > + }; > }; > > &avb { > @@ -104,6 +110,8 @@ channel0 { > }; > > &du { > + clocks = <&cpg CPG_MOD 724>, <&x1_clk>; > + clock-names = "du.0", "dclkin.0"; > status = "okay"; > }; > >
Hi Geert and Valentine, Thank you for the patch. On Tue, May 04, 2021 at 11:14:34AM +0200, Geert Uytterhoeven wrote: > From: Valentine Barshak <valentine.barshak@cogentembedded.com> > > This adds X1 clock which supplies a frequency of 148.5 MHz. > This clock is connected to the external dot clock input signal. > > Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> > [geert: Verified schematics] > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > --- > Untested due to lack of hardware > --- > arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts > index 874a7fc2730b00db..5c84681703edad2e 100644 > --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts > +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts > @@ -73,6 +73,12 @@ memory@48000000 { > /* first 128MB is reserved for secure area. */ > reg = <0x0 0x48000000 0x0 0x38000000>; > }; > + > + x1_clk: x1-clock { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <148500000>; > + }; > }; > > &avb { > @@ -104,6 +110,8 @@ channel0 { > }; > > &du { > + clocks = <&cpg CPG_MOD 724>, <&x1_clk>; > + clock-names = "du.0", "dclkin.0"; > status = "okay"; > }; >
diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index 874a7fc2730b00db..5c84681703edad2e 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -73,6 +73,12 @@ memory@48000000 { /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x38000000>; }; + + x1_clk: x1-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; }; &avb { @@ -104,6 +110,8 @@ channel0 { }; &du { + clocks = <&cpg CPG_MOD 724>, <&x1_clk>; + clock-names = "du.0", "dclkin.0"; status = "okay"; };