| Message ID | 20210512185441.3619828-29-matheus.ferst@eldorado.org.br (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Base for adding PowerPC 64-bit instructions | expand |
On 5/12/21 1:54 PM, matheus.ferst@eldorado.org.br wrote: > +static bool do_set_bool_cond(DisasContext *ctx, arg_X_bi *a, bool neg, bool rev) > +{ > + REQUIRE_INSNS_FLAGS2(ctx, ISA310); > + uint32_t mask = 0x08 >> (a->bi & 0x03); > + TCGv temp = tcg_temp_new(); > + > + tcg_gen_extu_i32_tl(temp, cpu_crf[a->bi >> 2]); > + tcg_gen_andi_tl(temp, temp, mask); > + tcg_gen_movcond_tl(a->r?TCG_COND_EQ:TCG_COND_NE, cpu_gpr[a->rt], temp, > + tcg_constant_tl(0), tcg_constant_tl(a->n?-1:1), > + tcg_constant_tl(0)); Mind the spacing around ?:. Did you forget to update a->r and a->n to "neg" and "rev"? It sure looks like this doesn't compile... I guess this is fine with movcond, but perhaps slightly better with tcg_gen_setcondi_tl(cond, rt, temp, 0); if (neg) { tcg_gen_neg_tl(rt, rt); } TCG isn't the most optimizing of compilers... r~
On 13/05/2021 08:01, Richard Henderson wrote: > On 5/12/21 1:54 PM, matheus.ferst@eldorado.org.br wrote: >> +static bool do_set_bool_cond(DisasContext *ctx, arg_X_bi *a, bool >> neg, bool rev) >> +{ >> + REQUIRE_INSNS_FLAGS2(ctx, ISA310); >> + uint32_t mask = 0x08 >> (a->bi & 0x03); >> + TCGv temp = tcg_temp_new(); >> + >> + tcg_gen_extu_i32_tl(temp, cpu_crf[a->bi >> 2]); >> + tcg_gen_andi_tl(temp, temp, mask); >> + tcg_gen_movcond_tl(a->r?TCG_COND_EQ:TCG_COND_NE, cpu_gpr[a->rt], >> temp, >> + tcg_constant_tl(0), tcg_constant_tl(a->n?-1:1), >> + tcg_constant_tl(0)); > > Mind the spacing around ?:. > Fixed. > Did you forget to update a->r and a->n to "neg" and "rev"? > It sure looks like this doesn't compile... > I messed up when rebasing, the change is in the next patch. I'll fix that too. > I guess this is fine with movcond, but perhaps slightly better with > > tcg_gen_setcondi_tl(cond, rt, temp, 0); > if (neg) { > tcg_gen_neg_tl(rt, rt); > } > > TCG isn't the most optimizing of compilers... > > > r~ And also looks cleaner, I'll apply that too.
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 8460100177..d69c0bc14c 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -26,6 +26,9 @@ &X rt ra rb @X ...... rt:5 ra:5 rb:5 .......... . &X +&X_bi rt bi +@X_bi ...... rt:5 bi:5 ----- .......... - &X_bi + ### Fixed-Point Load Instructions LBZ 100010 ..... ..... ................ @D @@ -83,3 +86,10 @@ STDUX 011111 ..... ..... ..... 0010110101 - @X ADDI 001110 ..... ..... ................ @D ADDIS 001111 ..... ..... ................ @D + +### Move To/From System Register Instructions + +SETBC 011111 ..... ..... ----- 0110000000 - @X_bi +SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi +SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi +SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc index 04a974214f..37dd25148c 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -201,3 +201,24 @@ static bool trans_PNOP(DisasContext *ctx, arg_PNOP *a) } return true; } + +static bool do_set_bool_cond(DisasContext *ctx, arg_X_bi *a, bool neg, bool rev) +{ + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + uint32_t mask = 0x08 >> (a->bi & 0x03); + TCGv temp = tcg_temp_new(); + + tcg_gen_extu_i32_tl(temp, cpu_crf[a->bi >> 2]); + tcg_gen_andi_tl(temp, temp, mask); + tcg_gen_movcond_tl(a->r?TCG_COND_EQ:TCG_COND_NE, cpu_gpr[a->rt], temp, + tcg_constant_tl(0), tcg_constant_tl(a->n?-1:1), + tcg_constant_tl(0)); + tcg_temp_free(temp); + + return true; +} + +TRANS(SETBC, do_set_bool_cond, false, false) +TRANS(SETBCR, do_set_bool_cond, false, true) +TRANS(SETNBC, do_set_bool_cond, true, false) +TRANS(SETNBCR, do_set_bool_cond, true, true)