| Message ID | 20210515031035.2561658-11-matthew.d.roper@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Alder Lake-P Support | expand |
On Fri, May 14, 2021 at 08:10:22PM -0700, Matt Roper wrote: > From: José Roberto de Souza <jose.souza@intel.com> > > Alderlake-P don't have programing sequences for MBUS or DBUF during > display initializaiton, instead it requires programing to those > registers during modeset because it to depend on the pipes left > enabled. Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > > Bspec: 49213 > Cc: Matt Roper <matthew.d.roper@intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display_power.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > index 29d2f1d0cffd..26d2eba87486 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -5246,6 +5246,9 @@ static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv) > { > enum dbuf_slice slice; > > + if (IS_ALDERLAKE_P(dev_priv)) > + return; > + > for_each_dbuf_slice(dev_priv, slice) > intel_de_rmw(dev_priv, DBUF_CTL_S(slice), > DBUF_TRACKER_STATE_SERVICE_MASK, > @@ -5257,6 +5260,9 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv) > unsigned long abox_regs = INTEL_INFO(dev_priv)->abox_mask; > u32 mask, val, i; > > + if (IS_ALDERLAKE_P(dev_priv)) > + return; > + > mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK | > MBUS_ABOX_BT_CREDIT_POOL2_MASK | > MBUS_ABOX_B_CREDIT_MASK | > -- > 2.25.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 29d2f1d0cffd..26d2eba87486 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -5246,6 +5246,9 @@ static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv) { enum dbuf_slice slice; + if (IS_ALDERLAKE_P(dev_priv)) + return; + for_each_dbuf_slice(dev_priv, slice) intel_de_rmw(dev_priv, DBUF_CTL_S(slice), DBUF_TRACKER_STATE_SERVICE_MASK, @@ -5257,6 +5260,9 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv) unsigned long abox_regs = INTEL_INFO(dev_priv)->abox_mask; u32 mask, val, i; + if (IS_ALDERLAKE_P(dev_priv)) + return; + mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK | MBUS_ABOX_BT_CREDIT_POOL2_MASK | MBUS_ABOX_B_CREDIT_MASK |