| Message ID | fb8b3df3a25120cb1ae9adfd25c754334e8eaf4e.1621097174.git.noodles@earth.li (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | ARM: dts: qcom: Enable various devices for IPQ806x / RB3011 | expand |
On 15-05-21, 17:52, Jonathan McDowell wrote: > Now the ADM driver is in mainline add the appropriate definitions for it > and the NAND controller to get NAND working on IPQ806x platforms, > > Signed-off-by: Jonathan McDowell <noodles@earth.li> > --- > arch/arm/boot/dts/qcom-ipq8064.dtsi | 67 +++++++++++++++++++++++++++++ > 1 file changed, 67 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi > index 98995ead4413..aaab3820ab0b 100644 > --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi > +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi > @@ -185,6 +185,31 @@ > bias-pull-up; > }; > }; > + > + nand_pins: nand_pins { > + mux { > + pins = "gpio34", "gpio35", "gpio36", > + "gpio37", "gpio38", "gpio39", > + "gpio40", "gpio41", "gpio42", > + "gpio43", "gpio44", "gpio45", > + "gpio46", "gpio47"; > + function = "nand"; > + drive-strength = <10>; > + bias-disable; > + }; > + > + pullups { > + pins = "gpio39"; > + bias-pull-up; > + }; > + > + hold { > + pins = "gpio40", "gpio41", "gpio42", > + "gpio43", "gpio44", "gpio45", > + "gpio46", "gpio47"; > + bias-bus-hold; > + }; > + }; > }; > > intc: interrupt-controller@2000000 { > @@ -226,6 +251,26 @@ > reg = <0x02098000 0x1000>, <0x02008000 0x1000>; > }; > > + adm_dma: dma@18300000 { dma-controller@...
On Mon, May 17, 2021 at 03:10:43PM +0530, Vinod Koul wrote: > On 15-05-21, 17:52, Jonathan McDowell wrote: > > Now the ADM driver is in mainline add the appropriate definitions for it > > and the NAND controller to get NAND working on IPQ806x platforms, > > > > Signed-off-by: Jonathan McDowell <noodles@earth.li> > > --- > > arch/arm/boot/dts/qcom-ipq8064.dtsi | 67 +++++++++++++++++++++++++++++ > > 1 file changed, 67 insertions(+) > > > > diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi > > index 98995ead4413..aaab3820ab0b 100644 > > --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi > > +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi > > @@ -185,6 +185,31 @@ > > bias-pull-up; > > }; > > }; > > + > > + nand_pins: nand_pins { > > + mux { > > + pins = "gpio34", "gpio35", "gpio36", > > + "gpio37", "gpio38", "gpio39", > > + "gpio40", "gpio41", "gpio42", > > + "gpio43", "gpio44", "gpio45", > > + "gpio46", "gpio47"; > > + function = "nand"; > > + drive-strength = <10>; > > + bias-disable; > > + }; > > + > > + pullups { > > + pins = "gpio39"; > > + bias-pull-up; > > + }; > > + > > + hold { > > + pins = "gpio40", "gpio41", "gpio42", > > + "gpio43", "gpio44", "gpio45", > > + "gpio46", "gpio47"; > > + bias-bus-hold; > > + }; > > + }; > > }; > > > > intc: interrupt-controller@2000000 { > > @@ -226,6 +251,26 @@ > > reg = <0x02098000 0x1000>, <0x02008000 0x1000>; > > }; > > > > + adm_dma: dma@18300000 { > > dma-controller@... Thanks, will fix for v2. J.
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 98995ead4413..aaab3820ab0b 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -185,6 +185,31 @@ bias-pull-up; }; }; + + nand_pins: nand_pins { + mux { + pins = "gpio34", "gpio35", "gpio36", + "gpio37", "gpio38", "gpio39", + "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47"; + function = "nand"; + drive-strength = <10>; + bias-disable; + }; + + pullups { + pins = "gpio39"; + bias-pull-up; + }; + + hold { + pins = "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47"; + bias-bus-hold; + }; + }; }; intc: interrupt-controller@2000000 { @@ -226,6 +251,26 @@ reg = <0x02098000 0x1000>, <0x02008000 0x1000>; }; + adm_dma: dma@18300000 { + compatible = "qcom,adm"; + reg = <0x18300000 0x100000>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + + clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; + clock-names = "core", "iface"; + + resets = <&gcc ADM0_RESET>, + <&gcc ADM0_PBUS_RESET>, + <&gcc ADM0_C0_RESET>, + <&gcc ADM0_C1_RESET>, + <&gcc ADM0_C2_RESET>; + reset-names = "clk", "pbus", "c0", "c1", "c2"; + qcom,ee = <0>; + + status = "disabled"; + }; + saw0: regulator@2089000 { compatible = "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; @@ -403,6 +448,28 @@ status = "disabled"; }; + nand: nand-controller@1ac00000 { + compatible = "qcom,ipq806x-nand"; + reg = <0x1ac00000 0x800>; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + clocks = <&gcc EBI2_CLK>, + <&gcc EBI2_AON_CLK>; + clock-names = "core", "aon"; + + dmas = <&adm_dma 3>; + dma-names = "rxtx"; + qcom,cmd-crci = <15>; + qcom,data-crci = <3>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + sata: sata@29000000 { compatible = "qcom,ipq806x-ahci", "generic-ahci"; reg = <0x29000000 0x180>;
Now the ADM driver is in mainline add the appropriate definitions for it and the NAND controller to get NAND working on IPQ806x platforms, Signed-off-by: Jonathan McDowell <noodles@earth.li> --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 67 +++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+)