| Message ID | 20210520124406.2731873-10-tabba@google.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Tidy up cache.S | expand |
On Thu, May 20, 2021 at 01:43:57PM +0100, Fuad Tabba wrote: > Many comments refer to the function flush_icache_range, where the > intent is in fact __flush_icache_range. Fix these comments to > refer to the intended function. > > That's probably due to commit 3b8c9f1cdfc506e9 ("arm64: IPI each > CPU after invalidating the I-cache for kernel mappings"), which > renamed flush_icache_range() to __flush_icache_range() and added > a wrapper. > > No functional change intended. > > Signed-off-by: Fuad Tabba <tabba@google.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Mark. > --- > arch/arm64/kernel/hibernate-asm.S | 4 ++-- > arch/arm64/mm/cache.S | 2 +- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/kernel/hibernate-asm.S b/arch/arm64/kernel/hibernate-asm.S > index 0ed2f72a6b94..ef2ab7caf815 100644 > --- a/arch/arm64/kernel/hibernate-asm.S > +++ b/arch/arm64/kernel/hibernate-asm.S > @@ -45,7 +45,7 @@ > * Because this code has to be copied to a 'safe' page, it can't call out to > * other functions by PC-relative address. Also remember that it may be > * mid-way through over-writing other functions. For this reason it contains > - * code from flush_icache_range() and uses the copy_page() macro. > + * code from __flush_icache_range() and uses the copy_page() macro. > * > * This 'safe' page is mapped via ttbr0, and executed from there. This function > * switches to a copy of the linear map in ttbr1, performs the restore, then > @@ -87,7 +87,7 @@ SYM_CODE_START(swsusp_arch_suspend_exit) > copy_page x0, x1, x2, x3, x4, x5, x6, x7, x8, x9 > > add x1, x10, #PAGE_SIZE > - /* Clean the copied page to PoU - based on flush_icache_range() */ > + /* Clean the copied page to PoU - based on __flush_icache_range() */ > raw_dcache_line_size x2, x3 > sub x3, x2, #1 > bic x4, x10, x3 > diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S > index 7318a40dd6ca..80da4b8718b6 100644 > --- a/arch/arm64/mm/cache.S > +++ b/arch/arm64/mm/cache.S > @@ -50,7 +50,7 @@ alternative_else_nop_endif > .endm > > /* > - * flush_icache_range(start,end) > + * __flush_icache_range(start,end) > * > * Ensure that the I and D caches are coherent within specified region. > * This is typically used when code has been written to a memory region, > -- > 2.31.1.751.gd2f1c929bd-goog >
diff --git a/arch/arm64/kernel/hibernate-asm.S b/arch/arm64/kernel/hibernate-asm.S index 0ed2f72a6b94..ef2ab7caf815 100644 --- a/arch/arm64/kernel/hibernate-asm.S +++ b/arch/arm64/kernel/hibernate-asm.S @@ -45,7 +45,7 @@ * Because this code has to be copied to a 'safe' page, it can't call out to * other functions by PC-relative address. Also remember that it may be * mid-way through over-writing other functions. For this reason it contains - * code from flush_icache_range() and uses the copy_page() macro. + * code from __flush_icache_range() and uses the copy_page() macro. * * This 'safe' page is mapped via ttbr0, and executed from there. This function * switches to a copy of the linear map in ttbr1, performs the restore, then @@ -87,7 +87,7 @@ SYM_CODE_START(swsusp_arch_suspend_exit) copy_page x0, x1, x2, x3, x4, x5, x6, x7, x8, x9 add x1, x10, #PAGE_SIZE - /* Clean the copied page to PoU - based on flush_icache_range() */ + /* Clean the copied page to PoU - based on __flush_icache_range() */ raw_dcache_line_size x2, x3 sub x3, x2, #1 bic x4, x10, x3 diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index 7318a40dd6ca..80da4b8718b6 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -50,7 +50,7 @@ alternative_else_nop_endif .endm /* - * flush_icache_range(start,end) + * __flush_icache_range(start,end) * * Ensure that the I and D caches are coherent within specified region. * This is typically used when code has been written to a memory region,
Many comments refer to the function flush_icache_range, where the intent is in fact __flush_icache_range. Fix these comments to refer to the intended function. That's probably due to commit 3b8c9f1cdfc506e9 ("arm64: IPI each CPU after invalidating the I-cache for kernel mappings"), which renamed flush_icache_range() to __flush_icache_range() and added a wrapper. No functional change intended. Signed-off-by: Fuad Tabba <tabba@google.com> --- arch/arm64/kernel/hibernate-asm.S | 4 ++-- arch/arm64/mm/cache.S | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-)