diff mbox series

linux-user: Handle EXCP10_COPR properly for i386

Message ID CAK8YQrXoOJNwfoutvh7BkYmqfdMtZ6eAQQ+uAjL27FuOK28cvg@mail.gmail.com (mailing list archive)
State New, archived
Headers show
Series linux-user: Handle EXCP10_COPR properly for i386 | expand

Commit Message

Xu Zou May 14, 2021, 9:23 a.m. UTC 
From e805b793f7d4b3e8c37d540b7d6cc0c6ac682311 Mon Sep 17 00:00:00 2001
From: Xu Zou <sendtozouxu@gmail.com>
Date: Fri, 14 May 2021 15:55:07 +0800
Subject: [PATCH] linux-user: Handle EXCP10_COPR properly for i386

Handle EXCP10_COPR properly for i386 in cpu loop.

NE flag is set to select native mode for handling floating-point
exceptions. FWAIT instruction can raise EXCP10_COPR exception by using
fpu_raise_exception() function.

The code is based on kernel's function fpu__exception_code() in
arch/x86/kernel/fpu/core.c.

Signed-off-by: Xu Zou <sendtozouxu@gmail.com>
---
 linux-user/i386/cpu_loop.c | 26 +++++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

aborting\n",
@@ -327,7 +351,7 @@ void cpu_loop(CPUX86State *env)

 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
 {
-    env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
+    env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK | CR0_NE_MASK;
     env->hflags |= HF_PE_MASK | HF_CPL_MASK;
     if (env->features[FEAT_1_EDX] & CPUID_SSE) {
         env->cr[4] |= CR4_OSFXSR_MASK;

Comments

Xu Zou May 21, 2021, 3:04 a.m. UTC | #1 
ping

邹旭 <sendtozouxu@gmail.com> 于2021年5月14日周五 下午5:23写道：

> From e805b793f7d4b3e8c37d540b7d6cc0c6ac682311 Mon Sep 17 00:00:00 2001
> From: Xu Zou <sendtozouxu@gmail.com>
> Date: Fri, 14 May 2021 15:55:07 +0800
> Subject: [PATCH] linux-user: Handle EXCP10_COPR properly for i386
>
> Handle EXCP10_COPR properly for i386 in cpu loop.
>
> NE flag is set to select native mode for handling floating-point
> exceptions. FWAIT instruction can raise EXCP10_COPR exception by using
> fpu_raise_exception() function.
>
> The code is based on kernel's function fpu__exception_code() in
> arch/x86/kernel/fpu/core.c.
>
> Signed-off-by: Xu Zou <sendtozouxu@gmail.com>
> ---
>  linux-user/i386/cpu_loop.c | 26 +++++++++++++++++++++++++-
>  1 file changed, 25 insertions(+), 1 deletion(-)
>
> diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c
> index f813e87294..e1f2911554 100644
> --- a/linux-user/i386/cpu_loop.c
> +++ b/linux-user/i386/cpu_loop.c
> @@ -199,6 +199,8 @@ void cpu_loop(CPUX86State *env)
>  {
>      CPUState *cs = env_cpu(env);
>      int trapnr;
> +    int si_code;
> +    uint8_t status;
>      abi_ulong pc;
>      abi_ulong ret;
>
> @@ -315,6 +317,28 @@ void cpu_loop(CPUX86State *env)
>          case EXCP_ATOMIC:
>              cpu_exec_step_atomic(cs);
>              break;
> +        case EXCP10_COPR:
> +            si_code = 0;
> +            status = env->fp_status.float_exception_flags;
> +            if (status & float_flag_invalid) {
> +                si_code = TARGET_FPE_FLTINV;
> +            }
> +            if (status & float_flag_divbyzero) {
> +                si_code = TARGET_FPE_FLTDIV;
> +            }
> +            if (status & float_flag_overflow) {
> +                si_code = TARGET_FPE_FLTOVF;
> +            }
> +            if ((status & float_flag_underflow) ||
> +                (status & float_flag_input_denormal) ||
> +                (status & float_flag_output_denormal)) {
> +                si_code = TARGET_FPE_FLTUND;
> +            }
> +            if (status & float_flag_inexact) {
> +                si_code = TARGET_FPE_FLTRES;
> +            }
> +            gen_signal(env, TARGET_SIGFPE, si_code, env->eip);
> +            break;
>          default:
>              pc = env->segs[R_CS].base + env->eip;
>              EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x -
> aborting\n",
> @@ -327,7 +351,7 @@ void cpu_loop(CPUX86State *env)
>
>  void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
>  {
> -    env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
> +    env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK | CR0_NE_MASK;
>      env->hflags |= HF_PE_MASK | HF_CPL_MASK;
>      if (env->features[FEAT_1_EDX] & CPUID_SSE) {
>          env->cr[4] |= CR4_OSFXSR_MASK;
> --
> 2.25.1
>
>
diff mbox series

Patch

diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c
index f813e87294..e1f2911554 100644
--- a/linux-user/i386/cpu_loop.c
+++ b/linux-user/i386/cpu_loop.c
@@ -199,6 +199,8 @@  void cpu_loop(CPUX86State *env)
 {
     CPUState *cs = env_cpu(env);
     int trapnr;
+    int si_code;
+    uint8_t status;
     abi_ulong pc;
     abi_ulong ret;

@@ -315,6 +317,28 @@  void cpu_loop(CPUX86State *env)
         case EXCP_ATOMIC:
             cpu_exec_step_atomic(cs);
             break;
+        case EXCP10_COPR:
+            si_code = 0;
+            status = env->fp_status.float_exception_flags;
+            if (status & float_flag_invalid) {
+                si_code = TARGET_FPE_FLTINV;
+            }
+            if (status & float_flag_divbyzero) {
+                si_code = TARGET_FPE_FLTDIV;
+            }
+            if (status & float_flag_overflow) {
+                si_code = TARGET_FPE_FLTOVF;
+            }
+            if ((status & float_flag_underflow) ||
+                (status & float_flag_input_denormal) ||
+                (status & float_flag_output_denormal)) {
+                si_code = TARGET_FPE_FLTUND;
+            }
+            if (status & float_flag_inexact) {
+                si_code = TARGET_FPE_FLTRES;
+            }
+            gen_signal(env, TARGET_SIGFPE, si_code, env->eip);
+            break;
         default:
             pc = env->segs[R_CS].base + env->eip;
             EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x -