| Message ID | 20210525010358.152808-1-richard.henderson@linaro.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | target/arm: Implement SVE2 | expand |
Patchew URL: https://patchew.org/QEMU/20210525010358.152808-1-richard.henderson@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210525010358.152808-1-richard.henderson@linaro.org
Subject: [PATCH v7 00/92] target/arm: Implement SVE2
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/20210525010358.152808-1-richard.henderson@linaro.org -> patchew/20210525010358.152808-1-richard.henderson@linaro.org
Switched to a new branch 'test'
c92f000 target/arm: Enable SVE2 and related extensions
69c800e linux-user/aarch64: Enable hwcap bits for sve2 and related extensions
01eda80 target/arm: Implement integer matrix multiply accumulate
14cc122 target/arm: Implement aarch32 VSUDOT, VUSDOT
0a65323 target/arm: Split decode of VSDOT and VUDOT
1941b29 target/arm: Split out do_neon_ddda
f7218e0 target/arm: Fix decode for VDOT (indexed)
9529cc6 target/arm: Remove unused fpst from VDOT_scalar
3ce0386 target/arm: Split out do_neon_ddda_fpst
1d7de85 target/arm: Implement aarch64 SUDOT, USDOT
dd1f6e8 target/arm: Implement SVE2 fp multiply-add long
5989493 target/arm: Move endian adjustment macros to vec_internal.h
d2a394e target/arm: Implement SVE2 bitwise shift immediate
d4e451b target/arm: Implement 128-bit ZIP, UZP, TRN
cf8b092 target/arm: Implement SVE2 LD1RO
d214a19 target/arm: Tidy do_ldrq
67ea69f target/arm: Share table of sve load functions
8c5f448 target/arm: Implement SVE2 FLOGB
816872f target/arm: Implement SVE2 FCVTXNT, FCVTX
48f2b22 target/arm: Implement SVE2 FCVTLT
e69a6dd target/arm: Implement SVE2 FCVTNT
4def475 target/arm: Implement SVE2 TBL, TBX
d506b3a target/arm: Implement SVE2 crypto constructive binary operations
1c998ce target/arm: Implement SVE2 crypto destructive binary operations
1970950 target/arm: Implement SVE2 crypto unary operations
9206764 target/arm: Implement SVE mixed sign dot product
5ea763f target/arm: Implement SVE mixed sign dot product (indexed)
2f5803a target/arm: Macroize helper_gvec_{s,u}dot_idx_{b,h}
83112aa target/arm: Macroize helper_gvec_{s,u}dot_{b,h}
159b350 target/arm: Implement SVE2 complex integer dot product
21c9d3b target/arm: Implement SVE2 complex integer multiply-add (indexed)
322bb04 target/arm: Implement SVE2 integer multiply long (indexed)
58ce7f2 target/arm: Implement SVE2 multiply-add long (indexed)
80fafdc target/arm: Implement SVE2 saturating multiply high (indexed)
e64d679 target/arm: Implement SVE2 signed saturating doubling multiply high
cf18b22 target/arm: Implement SVE2 saturating multiply (indexed)
19eb26e target/arm: Implement SVE2 saturating multiply-add (indexed)
1c9f4f1 target/arm: Implement SVE2 saturating multiply-add high (indexed)
3f2a3c3 target/arm: Implement SVE2 integer multiply-add (indexed)
bfca929 target/arm: Implement SVE2 integer multiply (indexed)
c4b5063 target/arm: Split out formats for 3 vectors + 1 index
194b523 target/arm: Split out formats for 2 vectors + 1 index
e0372f8 target/arm: Pass separate addend to FCMLA helpers
599a38f target/arm: Pass separate addend to {U, S}DOT helpers
f385927 target/arm: Use correct output type for gvec_sdot_*_b
22df8b0 target/arm: Implement SVE2 SPLICE, EXT
952e3b9 target/arm: Implement SVE2 FMMLA
5a516f9 target/arm: Implement SVE2 gather load insns
bb92adf target/arm: Implement SVE2 scatter store insns
e673ae8 target/arm: Implement SVE2 XAR
96aaa72 target/arm: Implement SVE2 HISTCNT, HISTSEG
90898ea target/arm: Implement SVE2 RSUBHNB, RSUBHNT
d8b4007 target/arm: Implement SVE2 SUBHNB, SUBHNT
db298a0 target/arm: Implement SVE2 RADDHNB, RADDHNT
72940b4 target/arm: Implement SVE2 ADDHNB, ADDHNT
a34cfbf target/arm: Implement SVE2 complex integer multiply-add
b4dae6e target/arm: Implement SVE2 integer multiply-add long
43a2c90 target/arm: Implement SVE2 saturating multiply-add high
6e27f44 target/arm: Implement SVE2 saturating multiply-add long
9705463 target/arm: Implement SVE2 MATCH, NMATCH
fcbbefe target/arm: Implement SVE2 bitwise ternary operations
ae3df35 target/arm: Implement SVE2 WHILERW, WHILEWR
3fae73d target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS
0547622 target/arm: Implement SVE2 SQSHRN, SQRSHRN
0dfa93e target/arm: Implement SVE2 UQSHRN, UQRSHRN
4cab3a7 target/arm: Implement SVE2 SQSHRUN, SQRSHRUN
468c3f7 target/arm: Implement SVE2 SHRN, RSHRN
fb19eea target/arm: Implement SVE2 floating-point pairwise
5b09dd6 target/arm: Implement SVE2 saturating extract narrow
48576f9 target/arm: Implement SVE2 integer absolute difference and accumulate
a696626 target/arm: Implement SVE2 bitwise shift and insert
fc08d8a target/arm: Implement SVE2 bitwise shift right and accumulate
81e999e target/arm: Implement SVE2 integer add/subtract long with carry
8dcc8fa target/arm: Implement SVE2 integer absolute difference and accumulate long
4e12c09 target/arm: Implement SVE2 complex integer add
fbd5e8b target/arm: Implement SVE2 bitwise permute
2971fb0 target/arm: Implement SVE2 bitwise exclusive-or interleaved
858a322 target/arm: Implement SVE2 bitwise shift left long
f258250 target/arm: Implement SVE2 PMULLB, PMULLT
e004223 target/arm: Implement SVE2 integer multiply long
3268cbb target/arm: Implement SVE2 integer add/subtract wide
f8e276d target/arm: Implement SVE2 integer add/subtract interleaved long
1c44ef4 target/arm: Implement SVE2 integer add/subtract long
ddbe54a target/arm: Implement SVE2 saturating add/subtract (predicated)
e594649 target/arm: Implement SVE2 integer pairwise arithmetic
754969e target/arm: Implement SVE2 integer halving add/subtract (predicated)
1854b53 target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated)
c89f7ce target/arm: Split out saturating/rounding shifts from neon
fac5c4c target/arm: Implement SVE2 integer unary operations (predicated)
067ace5 target/arm: Implement SVE2 integer pairwise add and accumulate long
7390d3d target/arm: Implement SVE2 Integer Multiply - Unpredicated
682538d target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2
=== OUTPUT BEGIN ===
1/92 Checking commit 682538dc4b8e (target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2)
2/92 Checking commit 7390d3d46262 (target/arm: Implement SVE2 Integer Multiply - Unpredicated)
3/92 Checking commit 067ace5dda71 (target/arm: Implement SVE2 integer pairwise add and accumulate long)
4/92 Checking commit fac5c4c3e603 (target/arm: Implement SVE2 integer unary operations (predicated))
5/92 Checking commit c89f7ce41d9c (target/arm: Split out saturating/rounding shifts from neon)
6/92 Checking commit 1854b53ebf60 (target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated))
7/92 Checking commit 754969e17ffd (target/arm: Implement SVE2 integer halving add/subtract (predicated))
8/92 Checking commit e594649a3a1c (target/arm: Implement SVE2 integer pairwise arithmetic)
9/92 Checking commit ddbe54a5652e (target/arm: Implement SVE2 saturating add/subtract (predicated))
10/92 Checking commit 1c44ef459b0c (target/arm: Implement SVE2 integer add/subtract long)
11/92 Checking commit f8e276d6eec1 (target/arm: Implement SVE2 integer add/subtract interleaved long)
12/92 Checking commit 3268cbb67cd8 (target/arm: Implement SVE2 integer add/subtract wide)
13/92 Checking commit e004223da127 (target/arm: Implement SVE2 integer multiply long)
14/92 Checking commit f258250f5615 (target/arm: Implement SVE2 PMULLB, PMULLT)
15/92 Checking commit 858a322acbff (target/arm: Implement SVE2 bitwise shift left long)
16/92 Checking commit 2971fb07de6d (target/arm: Implement SVE2 bitwise exclusive-or interleaved)
17/92 Checking commit fbd5e8b1d21c (target/arm: Implement SVE2 bitwise permute)
18/92 Checking commit 4e12c091ada0 (target/arm: Implement SVE2 complex integer add)
19/92 Checking commit 8dcc8fa30606 (target/arm: Implement SVE2 integer absolute difference and accumulate long)
20/92 Checking commit 81e999ed81c2 (target/arm: Implement SVE2 integer add/subtract long with carry)
21/92 Checking commit fc08d8af932a (target/arm: Implement SVE2 bitwise shift right and accumulate)
22/92 Checking commit a696626745d6 (target/arm: Implement SVE2 bitwise shift and insert)
23/92 Checking commit 48576f9373c5 (target/arm: Implement SVE2 integer absolute difference and accumulate)
24/92 Checking commit 5b09dd6c4fa5 (target/arm: Implement SVE2 saturating extract narrow)
25/92 Checking commit fb19eea143d5 (target/arm: Implement SVE2 floating-point pairwise)
26/92 Checking commit 468c3f7a4160 (target/arm: Implement SVE2 SHRN, RSHRN)
27/92 Checking commit 4cab3a7e7572 (target/arm: Implement SVE2 SQSHRUN, SQRSHRUN)
28/92 Checking commit 0dfa93e8f75a (target/arm: Implement SVE2 UQSHRN, UQRSHRN)
29/92 Checking commit 05476225f3d5 (target/arm: Implement SVE2 SQSHRN, SQRSHRN)
30/92 Checking commit 3fae73d7d5f7 (target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS)
31/92 Checking commit ae3df357c4aa (target/arm: Implement SVE2 WHILERW, WHILEWR)
32/92 Checking commit fcbbefe01863 (target/arm: Implement SVE2 bitwise ternary operations)
33/92 Checking commit 970546347c56 (target/arm: Implement SVE2 MATCH, NMATCH)
34/92 Checking commit 6e27f442d852 (target/arm: Implement SVE2 saturating multiply-add long)
35/92 Checking commit 43a2c90d6b70 (target/arm: Implement SVE2 saturating multiply-add high)
36/92 Checking commit b4dae6e07e1a (target/arm: Implement SVE2 integer multiply-add long)
37/92 Checking commit a34cfbfb23fb (target/arm: Implement SVE2 complex integer multiply-add)
38/92 Checking commit 72940b48bfc4 (target/arm: Implement SVE2 ADDHNB, ADDHNT)
39/92 Checking commit db298a06dcb9 (target/arm: Implement SVE2 RADDHNB, RADDHNT)
40/92 Checking commit d8b40074f09b (target/arm: Implement SVE2 SUBHNB, SUBHNT)
41/92 Checking commit 90898ead0347 (target/arm: Implement SVE2 RSUBHNB, RSUBHNT)
42/92 Checking commit 96aaa72f2128 (target/arm: Implement SVE2 HISTCNT, HISTSEG)
43/92 Checking commit e673ae89ecbe (target/arm: Implement SVE2 XAR)
44/92 Checking commit bb92adf60ef7 (target/arm: Implement SVE2 scatter store insns)
45/92 Checking commit 5a516f908e2d (target/arm: Implement SVE2 gather load insns)
46/92 Checking commit 952e3b99df0f (target/arm: Implement SVE2 FMMLA)
47/92 Checking commit 22df8b077cbd (target/arm: Implement SVE2 SPLICE, EXT)
48/92 Checking commit f3859276cd4f (target/arm: Use correct output type for gvec_sdot_*_b)
49/92 Checking commit 599a38f3ec38 (target/arm: Pass separate addend to {U, S}DOT helpers)
50/92 Checking commit e0372f874233 (target/arm: Pass separate addend to FCMLA helpers)
51/92 Checking commit 194b52300266 (target/arm: Split out formats for 2 vectors + 1 index)
52/92 Checking commit c4b5063802b0 (target/arm: Split out formats for 3 vectors + 1 index)
53/92 Checking commit bfca9294e1b7 (target/arm: Implement SVE2 integer multiply (indexed))
ERROR: spaces required around that '*' (ctx:WxV)
#75: FILE: target/arm/translate-sve.c:3860:
+ static bool NAME(DisasContext *s, arg_rrx_esz *a) \
^
total: 1 errors, 0 warnings, 61 lines checked
Patch 53/92 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
54/92 Checking commit 3f2a3c3e2075 (target/arm: Implement SVE2 integer multiply-add (indexed))
55/92 Checking commit 1c9f4f1be654 (target/arm: Implement SVE2 saturating multiply-add high (indexed))
56/92 Checking commit 19eb26edf417 (target/arm: Implement SVE2 saturating multiply-add (indexed))
57/92 Checking commit cf18b2238b0a (target/arm: Implement SVE2 saturating multiply (indexed))
ERROR: spaces required around that '*' (ctx:WxV)
#100: FILE: target/arm/translate-sve.c:3870:
+ static bool NAME(DisasContext *s, arg_rrx_esz *a) \
^
total: 1 errors, 0 warnings, 78 lines checked
Patch 57/92 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
58/92 Checking commit e64d679e54d6 (target/arm: Implement SVE2 signed saturating doubling multiply high)
59/92 Checking commit 80fafdce12da (target/arm: Implement SVE2 saturating multiply high (indexed))
60/92 Checking commit 58ce7f2db065 (target/arm: Implement SVE2 multiply-add long (indexed))
61/92 Checking commit 322bb047f0c5 (target/arm: Implement SVE2 integer multiply long (indexed))
62/92 Checking commit 21c9d3bda8c5 (target/arm: Implement SVE2 complex integer multiply-add (indexed))
ERROR: spaces required around that '*' (ctx:WxV)
#106: FILE: target/arm/translate-sve.c:3980:
+ static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
^
total: 1 errors, 0 warnings, 87 lines checked
Patch 62/92 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
63/92 Checking commit 159b350731b4 (target/arm: Implement SVE2 complex integer dot product)
64/92 Checking commit 83112aaedbaf (target/arm: Macroize helper_gvec_{s,u}dot_{b,h})
65/92 Checking commit 2f5803abb82f (target/arm: Macroize helper_gvec_{s,u}dot_idx_{b,h})
ERROR: space prohibited before that close parenthesis ')'
#185: FILE: target/arm/vec_helper.c:601:
+DO_DOT_IDX(gvec_sdot_idx_h, int64_t, int16_t, int16_t, )
ERROR: space prohibited before that close parenthesis ')'
#186: FILE: target/arm/vec_helper.c:602:
+DO_DOT_IDX(gvec_udot_idx_h, uint64_t, uint16_t, uint16_t, )
total: 2 errors, 0 warnings, 168 lines checked
Patch 65/92 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
66/92 Checking commit 5ea763f660f9 (target/arm: Implement SVE mixed sign dot product (indexed))
67/92 Checking commit 9206764ad682 (target/arm: Implement SVE mixed sign dot product)
68/92 Checking commit 1970950163cd (target/arm: Implement SVE2 crypto unary operations)
69/92 Checking commit 1c998ce07842 (target/arm: Implement SVE2 crypto destructive binary operations)
70/92 Checking commit d506b3aa3a4f (target/arm: Implement SVE2 crypto constructive binary operations)
71/92 Checking commit 4def47524a11 (target/arm: Implement SVE2 TBL, TBX)
ERROR: space prohibited before that close parenthesis ')'
#155: FILE: target/arm/sve_helper.c:3143:
+DO_TB(d, uint64_t, )
total: 1 errors, 0 warnings, 165 lines checked
Patch 71/92 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
72/92 Checking commit e69a6dda45c7 (target/arm: Implement SVE2 FCVTNT)
73/92 Checking commit 48f2b22ed1c5 (target/arm: Implement SVE2 FCVTLT)
74/92 Checking commit 816872f9dac5 (target/arm: Implement SVE2 FCVTXNT, FCVTX)
75/92 Checking commit 8c5f4480a70c (target/arm: Implement SVE2 FLOGB)
76/92 Checking commit 67ea69ff02cb (target/arm: Share table of sve load functions)
77/92 Checking commit d214a19d3311 (target/arm: Tidy do_ldrq)
78/92 Checking commit cf8b092c3151 (target/arm: Implement SVE2 LD1RO)
79/92 Checking commit d4e451b5e559 (target/arm: Implement 128-bit ZIP, UZP, TRN)
ERROR: space prohibited before that close parenthesis ')'
#77: FILE: target/arm/sve_helper.c:3504:
+DO_ZIP(sve2_zip_q, Int128, )
ERROR: space prohibited before that close parenthesis ')'
#114: FILE: target/arm/sve_helper.c:3533:
+DO_UZP(sve2_uzp_q, Int128, )
ERROR: space prohibited before that close parenthesis ')'
#131: FILE: target/arm/sve_helper.c:3556:
+DO_TRN(sve2_trn_q, Int128, )
total: 3 errors, 0 warnings, 178 lines checked
Patch 79/92 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
80/92 Checking commit d2a394edb6f5 (target/arm: Implement SVE2 bitwise shift immediate)
81/92 Checking commit 59894934abcd (target/arm: Move endian adjustment macros to vec_internal.h)
82/92 Checking commit dd1f6e846c19 (target/arm: Implement SVE2 fp multiply-add long)
83/92 Checking commit 1d7de85c6e75 (target/arm: Implement aarch64 SUDOT, USDOT)
84/92 Checking commit 3ce0386e67e6 (target/arm: Split out do_neon_ddda_fpst)
85/92 Checking commit 9529cc68d47b (target/arm: Remove unused fpst from VDOT_scalar)
86/92 Checking commit f7218e0e4ee3 (target/arm: Fix decode for VDOT (indexed))
87/92 Checking commit 1941b2951a9f (target/arm: Split out do_neon_ddda)
88/92 Checking commit 0a653238523e (target/arm: Split decode of VSDOT and VUDOT)
89/92 Checking commit 14cc122c7f5e (target/arm: Implement aarch32 VSUDOT, VUSDOT)
90/92 Checking commit 01eda8076d88 (target/arm: Implement integer matrix multiply accumulate)
91/92 Checking commit 69c800ec69dd (linux-user/aarch64: Enable hwcap bits for sve2 and related extensions)
92/92 Checking commit c92f00044fa7 (target/arm: Enable SVE2 and related extensions)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20210525010358.152808-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
On Tue, 25 May 2021 at 02:07, Richard Henderson <richard.henderson@linaro.org> wrote: > > Changes for v7: > * Incorporate patch review, some of which broke out new patches. > * Recover 4 patches which somehow got dropped during the v6 rebase. > This should have been caught by risu testing, but I must have > thought the rebase trivial enough to skip that step. Oops. > > The patches lacking r-b are: > > 06-target-arm-Implement-SVE2-saturating-rounding-bit.patch > 48-target-arm-Use-correct-output-type-for-gvec_sdot_.patch > 60-target-arm-Implement-SVE2-multiply-add-long-index.patch > 61-target-arm-Implement-SVE2-integer-multiply-long-i.patch > 62-target-arm-Implement-SVE2-complex-integer-multipl.patch > 63-target-arm-Implement-SVE2-complex-integer-dot-pro.patch > 64-target-arm-Macroize-helper_gvec_-s-u-dot_-b-h.patch > 65-target-arm-Macroize-helper_gvec_-s-u-dot_idx_-b-h.patch > 75-target-arm-Implement-SVE2-FLOGB.patch > 76-target-arm-Share-table-of-sve-load-functions.patch > 77-target-arm-Tidy-do_ldrq.patch > 81-target-arm-Move-endian-adjustment-macros-to-vec_i.patch > 86-target-arm-Fix-decode-for-VDOT-indexed.patch > 87-target-arm-Split-out-do_neon_ddda.patch > 92-target-arm-Enable-SVE2-and-related-extensions.patch > I've reviewed the patches that were missing review and applied the whole thing to target-arm.next; thanks. -- PMM
Changes for v7: * Incorporate patch review, some of which broke out new patches. * Recover 4 patches which somehow got dropped during the v6 rebase. This should have been caught by risu testing, but I must have thought the rebase trivial enough to skip that step. Oops. The patches lacking r-b are: 06-target-arm-Implement-SVE2-saturating-rounding-bit.patch 48-target-arm-Use-correct-output-type-for-gvec_sdot_.patch 60-target-arm-Implement-SVE2-multiply-add-long-index.patch 61-target-arm-Implement-SVE2-integer-multiply-long-i.patch 62-target-arm-Implement-SVE2-complex-integer-multipl.patch 63-target-arm-Implement-SVE2-complex-integer-dot-pro.patch 64-target-arm-Macroize-helper_gvec_-s-u-dot_-b-h.patch 65-target-arm-Macroize-helper_gvec_-s-u-dot_idx_-b-h.patch 75-target-arm-Implement-SVE2-FLOGB.patch 76-target-arm-Share-table-of-sve-load-functions.patch 77-target-arm-Tidy-do_ldrq.patch 81-target-arm-Move-endian-adjustment-macros-to-vec_i.patch 86-target-arm-Fix-decode-for-VDOT-indexed.patch 87-target-arm-Split-out-do_neon_ddda.patch 92-target-arm-Enable-SVE2-and-related-extensions.patch r~ Richard Henderson (75): target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2 target/arm: Implement SVE2 Integer Multiply - Unpredicated target/arm: Implement SVE2 integer pairwise add and accumulate long target/arm: Implement SVE2 integer unary operations (predicated) target/arm: Split out saturating/rounding shifts from neon target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated) target/arm: Implement SVE2 integer halving add/subtract (predicated) target/arm: Implement SVE2 integer pairwise arithmetic target/arm: Implement SVE2 saturating add/subtract (predicated) target/arm: Implement SVE2 integer add/subtract long target/arm: Implement SVE2 integer add/subtract interleaved long target/arm: Implement SVE2 integer add/subtract wide target/arm: Implement SVE2 integer multiply long target/arm: Implement SVE2 PMULLB, PMULLT target/arm: Implement SVE2 bitwise shift left long target/arm: Implement SVE2 bitwise exclusive-or interleaved target/arm: Implement SVE2 bitwise permute target/arm: Implement SVE2 complex integer add target/arm: Implement SVE2 integer absolute difference and accumulate long target/arm: Implement SVE2 integer add/subtract long with carry target/arm: Implement SVE2 bitwise shift right and accumulate target/arm: Implement SVE2 bitwise shift and insert target/arm: Implement SVE2 integer absolute difference and accumulate target/arm: Implement SVE2 saturating extract narrow target/arm: Implement SVE2 SHRN, RSHRN target/arm: Implement SVE2 SQSHRUN, SQRSHRUN target/arm: Implement SVE2 UQSHRN, UQRSHRN target/arm: Implement SVE2 SQSHRN, SQRSHRN target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS target/arm: Implement SVE2 WHILERW, WHILEWR target/arm: Implement SVE2 bitwise ternary operations target/arm: Implement SVE2 saturating multiply-add long target/arm: Implement SVE2 saturating multiply-add high target/arm: Implement SVE2 integer multiply-add long target/arm: Implement SVE2 complex integer multiply-add target/arm: Implement SVE2 XAR target/arm: Use correct output type for gvec_sdot_*_b target/arm: Pass separate addend to {U,S}DOT helpers target/arm: Pass separate addend to FCMLA helpers target/arm: Split out formats for 2 vectors + 1 index target/arm: Split out formats for 3 vectors + 1 index target/arm: Implement SVE2 integer multiply (indexed) target/arm: Implement SVE2 integer multiply-add (indexed) target/arm: Implement SVE2 saturating multiply-add high (indexed) target/arm: Implement SVE2 saturating multiply-add (indexed) target/arm: Implement SVE2 saturating multiply (indexed) target/arm: Implement SVE2 signed saturating doubling multiply high target/arm: Implement SVE2 saturating multiply high (indexed) target/arm: Implement SVE2 multiply-add long (indexed) target/arm: Implement SVE2 integer multiply long (indexed) target/arm: Implement SVE2 complex integer multiply-add (indexed) target/arm: Implement SVE2 complex integer dot product target/arm: Macroize helper_gvec_{s,u}dot_{b,h} target/arm: Macroize helper_gvec_{s,u}dot_idx_{b,h} target/arm: Implement SVE mixed sign dot product (indexed) target/arm: Implement SVE mixed sign dot product target/arm: Implement SVE2 crypto unary operations target/arm: Implement SVE2 crypto destructive binary operations target/arm: Implement SVE2 crypto constructive binary operations target/arm: Implement SVE2 FCVTNT target/arm: Share table of sve load functions target/arm: Tidy do_ldrq target/arm: Implement SVE2 LD1RO target/arm: Implement 128-bit ZIP, UZP, TRN target/arm: Move endian adjustment macros to vec_internal.h target/arm: Implement aarch64 SUDOT, USDOT target/arm: Split out do_neon_ddda_fpst target/arm: Remove unused fpst from VDOT_scalar target/arm: Fix decode for VDOT (indexed) target/arm: Split out do_neon_ddda target/arm: Split decode of VSDOT and VUDOT target/arm: Implement aarch32 VSUDOT, VUSDOT target/arm: Implement integer matrix multiply accumulate linux-user/aarch64: Enable hwcap bits for sve2 and related extensions target/arm: Enable SVE2 and related extensions Stephen Long (17): target/arm: Implement SVE2 floating-point pairwise target/arm: Implement SVE2 MATCH, NMATCH target/arm: Implement SVE2 ADDHNB, ADDHNT target/arm: Implement SVE2 RADDHNB, RADDHNT target/arm: Implement SVE2 SUBHNB, SUBHNT target/arm: Implement SVE2 RSUBHNB, RSUBHNT target/arm: Implement SVE2 HISTCNT, HISTSEG target/arm: Implement SVE2 scatter store insns target/arm: Implement SVE2 gather load insns target/arm: Implement SVE2 FMMLA target/arm: Implement SVE2 SPLICE, EXT target/arm: Implement SVE2 TBL, TBX target/arm: Implement SVE2 FCVTLT target/arm: Implement SVE2 FCVTXNT, FCVTX target/arm: Implement SVE2 FLOGB target/arm: Implement SVE2 bitwise shift immediate target/arm: Implement SVE2 fp multiply-add long target/arm/cpu.h | 66 + target/arm/helper-sve.h | 722 +++++++- target/arm/helper.h | 110 +- target/arm/translate-a64.h | 3 + target/arm/vec_internal.h | 167 ++ target/arm/neon-shared.decode | 24 +- target/arm/sve.decode | 574 +++++- linux-user/elfload.c | 10 + target/arm/cpu.c | 2 + target/arm/cpu64.c | 13 + target/arm/cpu_tcg.c | 1 + target/arm/helper.c | 3 +- target/arm/kvm64.c | 21 +- target/arm/neon_helper.c | 507 +----- target/arm/sve_helper.c | 2110 ++++++++++++++++++++-- target/arm/translate-a64.c | 111 +- target/arm/translate-neon.c | 231 ++- target/arm/translate-sve.c | 3200 +++++++++++++++++++++++++++++++-- target/arm/vec_helper.c | 887 ++++++--- 19 files changed, 7656 insertions(+), 1106 deletions(-)