| Message ID | 20210511182322.3830-2-catalin.marinas@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: Taint the kernel on different GMID_EL1.BS | expand |
On Tue, May 11, 2021 at 07:23:21PM +0100, Catalin Marinas wrote: > The architecture has been updated and the CTR_EL0, CNTFRQ_EL1, > DCZID_EL0, MIDR_EL1, REVIDR_EL1 registers are all 64-bit, even if most > of them have a RES0 top 32-bit. > > Change their type to u64 in struct cpuinfo_arm64. > > Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Mark. > --- > > CTR_EL0 gained a new field with MTE in the top 32-bit, TminLine. I have > no idea what software is supposed to do with this field. I even have a > Jira ticket from 2019 asking for it to be removed. So I don't think we > should bother adding the mask/checks for it to the kernel. > > arch/arm64/include/asm/cpu.h | 10 +++++----- > arch/arm64/kernel/cpuinfo.c | 2 +- > 2 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h > index 7faae6ff3ab4..fe5a8499ddc2 100644 > --- a/arch/arm64/include/asm/cpu.h > +++ b/arch/arm64/include/asm/cpu.h > @@ -15,11 +15,11 @@ > struct cpuinfo_arm64 { > struct cpu cpu; > struct kobject kobj; > - u32 reg_ctr; > - u32 reg_cntfrq; > - u32 reg_dczid; > - u32 reg_midr; > - u32 reg_revidr; > + u64 reg_ctr; > + u64 reg_cntfrq; > + u64 reg_dczid; > + u64 reg_midr; > + u64 reg_revidr; > > u64 reg_id_aa64dfr0; > u64 reg_id_aa64dfr1; > diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c > index 77605aec25fe..4bea701117d4 100644 > --- a/arch/arm64/kernel/cpuinfo.c > +++ b/arch/arm64/kernel/cpuinfo.c > @@ -246,7 +246,7 @@ static struct kobj_type cpuregs_kobj_type = { > struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \ > \ > if (info->reg_midr) \ > - return sprintf(buf, "0x%016x\n", info->reg_##_field); \ > + return sprintf(buf, "0x%016llx\n", info->reg_##_field); \ > else \ > return 0; \ > } \
On 11/05/2021 19:23, Catalin Marinas wrote: > The architecture has been updated and the CTR_EL0, CNTFRQ_EL1, > DCZID_EL0, MIDR_EL1, REVIDR_EL1 registers are all 64-bit, even if most > of them have a RES0 top 32-bit. > > Change their type to u64 in struct cpuinfo_arm64. > > Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com> > --- > > CTR_EL0 gained a new field with MTE in the top 32-bit, TminLine. I have > no idea what software is supposed to do with this field. I even have a > Jira ticket from 2019 asking for it to be removed. So I don't think we > should bother adding the mask/checks for it to the kernel. > > arch/arm64/include/asm/cpu.h | 10 +++++----- > arch/arm64/kernel/cpuinfo.c | 2 +- > 2 files changed, 6 insertions(+), 6 deletions(-) > Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Hi Catalin, On 2021/5/12 2:23, Catalin Marinas wrote: > The architecture has been updated and the CTR_EL0, CNTFRQ_EL1, s/CNTFRQ_EL1/CNTFRQ_EL0? > DCZID_EL0, MIDR_EL1, REVIDR_EL1 registers are all 64-bit, even if most > of them have a RES0 top 32-bit. > > Change their type to u64 in struct cpuinfo_arm64. > > Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com> > --- > > CTR_EL0 gained a new field with MTE in the top 32-bit, TminLine. I have > no idea what software is supposed to do with this field. I even have a > Jira ticket from 2019 asking for it to be removed. So I don't think we > should bother adding the mask/checks for it to the kernel. > > arch/arm64/include/asm/cpu.h | 10 +++++----- > arch/arm64/kernel/cpuinfo.c | 2 +- > 2 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h > index 7faae6ff3ab4..fe5a8499ddc2 100644 > --- a/arch/arm64/include/asm/cpu.h > +++ b/arch/arm64/include/asm/cpu.h > @@ -15,11 +15,11 @@ > struct cpuinfo_arm64 { > struct cpu cpu; > struct kobject kobj; > - u32 reg_ctr; > - u32 reg_cntfrq; > - u32 reg_dczid; > - u32 reg_midr; > - u32 reg_revidr; > + u64 reg_ctr; > + u64 reg_cntfrq; One more question: is it ok to change the function prototype to u64 also? For CNTFRQ_EL0, if the Arm ARM expand the clock to more than 4GHz and it will also work this change (arch_timer and watchdog shall change at the the same time). Thanks, Shaokun > + u64 reg_dczid; > + u64 reg_midr; > + u64 reg_revidr; > > u64 reg_id_aa64dfr0; > u64 reg_id_aa64dfr1; > diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c > index 77605aec25fe..4bea701117d4 100644 > --- a/arch/arm64/kernel/cpuinfo.c > +++ b/arch/arm64/kernel/cpuinfo.c > @@ -246,7 +246,7 @@ static struct kobj_type cpuregs_kobj_type = { > struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \ > \ > if (info->reg_midr) \ > - return sprintf(buf, "0x%016x\n", info->reg_##_field); \ > + return sprintf(buf, "0x%016llx\n", info->reg_##_field); \ > else \ > return 0; \ > } \ > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > . >
On Mon, May 24, 2021 at 09:31:24AM +0800, Shaokun Zhang wrote: > On 2021/5/12 2:23, Catalin Marinas wrote: > > diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h > > index 7faae6ff3ab4..fe5a8499ddc2 100644 > > --- a/arch/arm64/include/asm/cpu.h > > +++ b/arch/arm64/include/asm/cpu.h > > @@ -15,11 +15,11 @@ > > struct cpuinfo_arm64 { > > struct cpu cpu; > > struct kobject kobj; > > - u32 reg_ctr; > > - u32 reg_cntfrq; > > - u32 reg_dczid; > > - u32 reg_midr; > > - u32 reg_revidr; > > + u64 reg_ctr; > > + u64 reg_cntfrq; > > One more question: is it ok to change the function prototype to u64 also? > For CNTFRQ_EL0, if the Arm ARM expand the clock to more than 4GHz and it > will also work this change (arch_timer and watchdog shall change at the > the same time). I think I'll keep cntfrq as u32. It matches the function prototype and the arm32 code which shares the same driver. Also, from ARMv8.6, there's a requirement that CNTFRQ_EL0 is standardised at 1GHz.
diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h index 7faae6ff3ab4..fe5a8499ddc2 100644 --- a/arch/arm64/include/asm/cpu.h +++ b/arch/arm64/include/asm/cpu.h @@ -15,11 +15,11 @@ struct cpuinfo_arm64 { struct cpu cpu; struct kobject kobj; - u32 reg_ctr; - u32 reg_cntfrq; - u32 reg_dczid; - u32 reg_midr; - u32 reg_revidr; + u64 reg_ctr; + u64 reg_cntfrq; + u64 reg_dczid; + u64 reg_midr; + u64 reg_revidr; u64 reg_id_aa64dfr0; u64 reg_id_aa64dfr1; diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 77605aec25fe..4bea701117d4 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -246,7 +246,7 @@ static struct kobj_type cpuregs_kobj_type = { struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \ \ if (info->reg_midr) \ - return sprintf(buf, "0x%016x\n", info->reg_##_field); \ + return sprintf(buf, "0x%016llx\n", info->reg_##_field); \ else \ return 0; \ } \
The architecture has been updated and the CTR_EL0, CNTFRQ_EL1, DCZID_EL0, MIDR_EL1, REVIDR_EL1 registers are all 64-bit, even if most of them have a RES0 top 32-bit. Change their type to u64 in struct cpuinfo_arm64. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com> --- CTR_EL0 gained a new field with MTE in the top 32-bit, TminLine. I have no idea what software is supposed to do with this field. I even have a Jira ticket from 2019 asking for it to be removed. So I don't think we should bother adding the mask/checks for it to the kernel. arch/arm64/include/asm/cpu.h | 10 +++++----- arch/arm64/kernel/cpuinfo.c | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-)