diff mbox series

[6/6] clk: imx8qm: add clock valid resource checking

Message ID 20210423033334.3317992-6-aisheng.dong@nxp.com (mailing list archive)
State Awaiting Upstream, archived
Headers show
Series [1/6] dt-bindings: arm: imx: scu: fix naming typo of clk compatible string | expand

Commit Message

Dong Aisheng April 23, 2021, 3:33 a.m. UTC 
Add imx8qm clock valid resource checking mechanism

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
 drivers/clk/imx/Makefile          |   2 +-
 drivers/clk/imx/clk-imx8qm-rsrc.c | 116 ++++++++++++++++++++++++++++++
 drivers/clk/imx/clk-imx8qxp.c     |   1 +
 drivers/clk/imx/clk-scu.h         |   1 +
 4 files changed, 119 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/imx/clk-imx8qm-rsrc.c

Comments

Abel Vesa May 13, 2021, 7:17 a.m. UTC | #1 
On 21-04-23 11:33:34, Dong Aisheng wrote:
> Add imx8qm clock valid resource checking mechanism
> 
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>

> ---
>  drivers/clk/imx/Makefile          |   2 +-
>  drivers/clk/imx/clk-imx8qm-rsrc.c | 116 ++++++++++++++++++++++++++++++
>  drivers/clk/imx/clk-imx8qxp.c     |   1 +
>  drivers/clk/imx/clk-scu.h         |   1 +
>  4 files changed, 119 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/imx/clk-imx8qm-rsrc.c
> 
> diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
> index 2fdd2fff16c7..c24a2acbfa56 100644
> --- a/drivers/clk/imx/Makefile
> +++ b/drivers/clk/imx/Makefile
> @@ -28,7 +28,7 @@ obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
>  
>  obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o
>  clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \
> -				     clk-imx8qxp-rsrc.o
> +				     clk-imx8qxp-rsrc.o clk-imx8qm-rsrc.o
>  clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) += clk-lpcg-scu.o clk-imx8qxp-lpcg.o
>  
>  obj-$(CONFIG_CLK_IMX1)   += clk-imx1.o
> diff --git a/drivers/clk/imx/clk-imx8qm-rsrc.c b/drivers/clk/imx/clk-imx8qm-rsrc.c
> new file mode 100644
> index 000000000000..183a071cbf20
> --- /dev/null
> +++ b/drivers/clk/imx/clk-imx8qm-rsrc.c
> @@ -0,0 +1,116 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019-2021 NXP
> + *	Dong Aisheng <aisheng.dong@nxp.com>
> + */
> +
> +#include <dt-bindings/firmware/imx/rsrc.h>
> +
> +#include "clk-scu.h"
> +
> +/* Keep sorted in the ascending order */
> +static u32 imx8qm_clk_scu_rsrc_table[] = {
> +	IMX_SC_R_A53,
> +	IMX_SC_R_A72,
> +	IMX_SC_R_DC_0_VIDEO0,
> +	IMX_SC_R_DC_0_VIDEO1,
> +	IMX_SC_R_DC_0,
> +	IMX_SC_R_DC_0_PLL_0,
> +	IMX_SC_R_DC_0_PLL_1,
> +	IMX_SC_R_DC_1_VIDEO0,
> +	IMX_SC_R_DC_1_VIDEO1,
> +	IMX_SC_R_DC_1,
> +	IMX_SC_R_DC_1_PLL_0,
> +	IMX_SC_R_DC_1_PLL_1,
> +	IMX_SC_R_SPI_0,
> +	IMX_SC_R_SPI_1,
> +	IMX_SC_R_SPI_2,
> +	IMX_SC_R_SPI_3,
> +	IMX_SC_R_UART_0,
> +	IMX_SC_R_UART_1,
> +	IMX_SC_R_UART_2,
> +	IMX_SC_R_UART_3,
> +	IMX_SC_R_UART_4,
> +	IMX_SC_R_EMVSIM_0,
> +	IMX_SC_R_EMVSIM_1,
> +	IMX_SC_R_I2C_0,
> +	IMX_SC_R_I2C_1,
> +	IMX_SC_R_I2C_2,
> +	IMX_SC_R_I2C_3,
> +	IMX_SC_R_I2C_4,
> +	IMX_SC_R_ADC_0,
> +	IMX_SC_R_ADC_1,
> +	IMX_SC_R_FTM_0,
> +	IMX_SC_R_FTM_1,
> +	IMX_SC_R_CAN_0,
> +	IMX_SC_R_GPU_0_PID0,
> +	IMX_SC_R_GPU_1_PID0,
> +	IMX_SC_R_PWM_0,
> +	IMX_SC_R_PWM_1,
> +	IMX_SC_R_PWM_2,
> +	IMX_SC_R_PWM_3,
> +	IMX_SC_R_PWM_4,
> +	IMX_SC_R_PWM_5,
> +	IMX_SC_R_PWM_6,
> +	IMX_SC_R_PWM_7,
> +	IMX_SC_R_GPT_0,
> +	IMX_SC_R_GPT_1,
> +	IMX_SC_R_GPT_2,
> +	IMX_SC_R_GPT_3,
> +	IMX_SC_R_GPT_4,
> +	IMX_SC_R_FSPI_0,
> +	IMX_SC_R_FSPI_1,
> +	IMX_SC_R_SDHC_0,
> +	IMX_SC_R_SDHC_1,
> +	IMX_SC_R_SDHC_2,
> +	IMX_SC_R_ENET_0,
> +	IMX_SC_R_ENET_1,
> +	IMX_SC_R_MLB_0,
> +	IMX_SC_R_USB_2,
> +	IMX_SC_R_NAND,
> +	IMX_SC_R_LVDS_0,
> +	IMX_SC_R_LVDS_0_PWM_0,
> +	IMX_SC_R_LVDS_0_I2C_0,
> +	IMX_SC_R_LVDS_0_I2C_1,
> +	IMX_SC_R_LVDS_1,
> +	IMX_SC_R_LVDS_1_PWM_0,
> +	IMX_SC_R_LVDS_1_I2C_0,
> +	IMX_SC_R_LVDS_1_I2C_1,
> +	IMX_SC_R_M4_0_I2C,
> +	IMX_SC_R_M4_1_I2C,
> +	IMX_SC_R_AUDIO_PLL_0,
> +	IMX_SC_R_VPU_UART,
> +	IMX_SC_R_VPUCORE,
> +	IMX_SC_R_MIPI_0,
> +	IMX_SC_R_MIPI_0_PWM_0,
> +	IMX_SC_R_MIPI_0_I2C_0,
> +	IMX_SC_R_MIPI_0_I2C_1,
> +	IMX_SC_R_MIPI_1,
> +	IMX_SC_R_MIPI_1_PWM_0,
> +	IMX_SC_R_MIPI_1_I2C_0,
> +	IMX_SC_R_MIPI_1_I2C_1,
> +	IMX_SC_R_CSI_0,
> +	IMX_SC_R_CSI_0_PWM_0,
> +	IMX_SC_R_CSI_0_I2C_0,
> +	IMX_SC_R_CSI_1,
> +	IMX_SC_R_CSI_1_PWM_0,
> +	IMX_SC_R_CSI_1_I2C_0,
> +	IMX_SC_R_HDMI,
> +	IMX_SC_R_HDMI_I2S,
> +	IMX_SC_R_HDMI_I2C_0,
> +	IMX_SC_R_HDMI_PLL_0,
> +	IMX_SC_R_HDMI_RX,
> +	IMX_SC_R_HDMI_RX_BYPASS,
> +	IMX_SC_R_HDMI_RX_I2C_0,
> +	IMX_SC_R_AUDIO_PLL_1,
> +	IMX_SC_R_AUDIO_CLK_0,
> +	IMX_SC_R_AUDIO_CLK_1,
> +	IMX_SC_R_HDMI_RX_PWM_0,
> +	IMX_SC_R_HDMI_PLL_1,
> +	IMX_SC_R_VPU,
> +};
> +
> +const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm = {
> +	.rsrc = imx8qm_clk_scu_rsrc_table,
> +	.num = ARRAY_SIZE(imx8qm_clk_scu_rsrc_table),
> +};
> diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
> index 9e35ae45b3a0..88cc737ee125 100644
> --- a/drivers/clk/imx/clk-imx8qxp.c
> +++ b/drivers/clk/imx/clk-imx8qxp.c
> @@ -134,6 +134,7 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
>  static const struct of_device_id imx8qxp_match[] = {
>  	{ .compatible = "fsl,scu-clk", },
>  	{ .compatible = "fsl,imx8qxp-clk", &imx_clk_scu_rsrc_imx8qxp, },
> +	{ .compatible = "fsl,imx8qm-clk", &imx_clk_scu_rsrc_imx8qm, },
>  	{ /* sentinel */ }
>  };
>  
> diff --git a/drivers/clk/imx/clk-scu.h b/drivers/clk/imx/clk-scu.h
> index bcacd8b1d1ab..22156e93b85d 100644
> --- a/drivers/clk/imx/clk-scu.h
> +++ b/drivers/clk/imx/clk-scu.h
> @@ -22,6 +22,7 @@ struct imx_clk_scu_rsrc_table {
>  extern struct list_head imx_scu_clks[];
>  extern const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops;
>  extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp;
> +extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm;
>  
>  int imx_clk_scu_init(struct device_node *np,
>  		     const struct imx_clk_scu_rsrc_table *data);
> -- 
> 2.25.1
>
Stephen Boyd June 2, 2021, 1:50 a.m. UTC | #2 
Quoting Dong Aisheng (2021-04-22 20:33:34)
> diff --git a/drivers/clk/imx/clk-imx8qm-rsrc.c b/drivers/clk/imx/clk-imx8qm-rsrc.c
> new file mode 100644
> index 000000000000..183a071cbf20
> --- /dev/null
> +++ b/drivers/clk/imx/clk-imx8qm-rsrc.c
> @@ -0,0 +1,116 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019-2021 NXP
> + *     Dong Aisheng <aisheng.dong@nxp.com>
> + */
> +
> +#include <dt-bindings/firmware/imx/rsrc.h>
> +
> +#include "clk-scu.h"
> +
> +/* Keep sorted in the ascending order */
> +static u32 imx8qm_clk_scu_rsrc_table[] = {

const?

> +       IMX_SC_R_A53,
Abel Vesa June 4, 2021, 6:46 a.m. UTC | #3 
On 21-06-01 18:50:06, Stephen Boyd wrote:
> Quoting Dong Aisheng (2021-04-22 20:33:34)
> > diff --git a/drivers/clk/imx/clk-imx8qm-rsrc.c b/drivers/clk/imx/clk-imx8qm-rsrc.c
> > new file mode 100644
> > index 000000000000..183a071cbf20
> > --- /dev/null
> > +++ b/drivers/clk/imx/clk-imx8qm-rsrc.c
> > @@ -0,0 +1,116 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2019-2021 NXP
> > + *     Dong Aisheng <aisheng.dong@nxp.com>
> > + */
> > +
> > +#include <dt-bindings/firmware/imx/rsrc.h>
> > +
> > +#include "clk-scu.h"
> > +
> > +/* Keep sorted in the ascending order */
> > +static u32 imx8qm_clk_scu_rsrc_table[] = {
> 
> const?
> 

Aisheng, no need to resend, I'll fold that in.

> > +       IMX_SC_R_A53,
Dong Aisheng June 4, 2021, 7:04 a.m. UTC | #4 
On Fri, Jun 4, 2021 at 2:46 PM Abel Vesa <abel.vesa@nxp.com> wrote:
>
> On 21-06-01 18:50:06, Stephen Boyd wrote:
> > Quoting Dong Aisheng (2021-04-22 20:33:34)
> > > diff --git a/drivers/clk/imx/clk-imx8qm-rsrc.c b/drivers/clk/imx/clk-imx8qm-rsrc.c
> > > new file mode 100644
> > > index 000000000000..183a071cbf20
> > > --- /dev/null
> > > +++ b/drivers/clk/imx/clk-imx8qm-rsrc.c
> > > @@ -0,0 +1,116 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Copyright 2019-2021 NXP
> > > + *     Dong Aisheng <aisheng.dong@nxp.com>
> > > + */
> > > +
> > > +#include <dt-bindings/firmware/imx/rsrc.h>
> > > +
> > > +#include "clk-scu.h"
> > > +
> > > +/* Keep sorted in the ascending order */
> > > +static u32 imx8qm_clk_scu_rsrc_table[] = {
> >
> > const?

Stephen,
Thanks for pointing this out

> >
>
> Aisheng, no need to resend, I'll fold that in.

Thanks

Regards
Aisheng

>
> > > +       IMX_SC_R_A53,
Abel Vesa June 4, 2021, 8:20 a.m. UTC | #5 
On 21-06-04 15:04:03, Dong Aisheng wrote:
> On Fri, Jun 4, 2021 at 2:46 PM Abel Vesa <abel.vesa@nxp.com> wrote:
> >
> > On 21-06-01 18:50:06, Stephen Boyd wrote:
> > > Quoting Dong Aisheng (2021-04-22 20:33:34)
> > > > diff --git a/drivers/clk/imx/clk-imx8qm-rsrc.c b/drivers/clk/imx/clk-imx8qm-rsrc.c
> > > > new file mode 100644
> > > > index 000000000000..183a071cbf20
> > > > --- /dev/null
> > > > +++ b/drivers/clk/imx/clk-imx8qm-rsrc.c
> > > > @@ -0,0 +1,116 @@
> > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > +/*
> > > > + * Copyright 2019-2021 NXP
> > > > + *     Dong Aisheng <aisheng.dong@nxp.com>
> > > > + */
> > > > +
> > > > +#include <dt-bindings/firmware/imx/rsrc.h>
> > > > +
> > > > +#include "clk-scu.h"
> > > > +
> > > > +/* Keep sorted in the ascending order */
> > > > +static u32 imx8qm_clk_scu_rsrc_table[] = {
> > >
> > > const?
> 
> Stephen,
> Thanks for pointing this out
> 
> > >
> >
> > Aisheng, no need to resend, I'll fold that in.
> 
> Thanks
> 

Applied all and folded the const change in.

Thanks.

> Regards
> Aisheng
> 
> >
> > > > +       IMX_SC_R_A53,
diff mbox series

Patch

diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 2fdd2fff16c7..c24a2acbfa56 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -28,7 +28,7 @@  obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
 
 obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o
 clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \
-				     clk-imx8qxp-rsrc.o
+				     clk-imx8qxp-rsrc.o clk-imx8qm-rsrc.o
 clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) += clk-lpcg-scu.o clk-imx8qxp-lpcg.o
 
 obj-$(CONFIG_CLK_IMX1)   += clk-imx1.o
diff --git a/drivers/clk/imx/clk-imx8qm-rsrc.c b/drivers/clk/imx/clk-imx8qm-rsrc.c
new file mode 100644
index 000000000000..183a071cbf20
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8qm-rsrc.c
@@ -0,0 +1,116 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ *	Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+#include "clk-scu.h"
+
+/* Keep sorted in the ascending order */
+static u32 imx8qm_clk_scu_rsrc_table[] = {
+	IMX_SC_R_A53,
+	IMX_SC_R_A72,
+	IMX_SC_R_DC_0_VIDEO0,
+	IMX_SC_R_DC_0_VIDEO1,
+	IMX_SC_R_DC_0,
+	IMX_SC_R_DC_0_PLL_0,
+	IMX_SC_R_DC_0_PLL_1,
+	IMX_SC_R_DC_1_VIDEO0,
+	IMX_SC_R_DC_1_VIDEO1,
+	IMX_SC_R_DC_1,
+	IMX_SC_R_DC_1_PLL_0,
+	IMX_SC_R_DC_1_PLL_1,
+	IMX_SC_R_SPI_0,
+	IMX_SC_R_SPI_1,
+	IMX_SC_R_SPI_2,
+	IMX_SC_R_SPI_3,
+	IMX_SC_R_UART_0,
+	IMX_SC_R_UART_1,
+	IMX_SC_R_UART_2,
+	IMX_SC_R_UART_3,
+	IMX_SC_R_UART_4,
+	IMX_SC_R_EMVSIM_0,
+	IMX_SC_R_EMVSIM_1,
+	IMX_SC_R_I2C_0,
+	IMX_SC_R_I2C_1,
+	IMX_SC_R_I2C_2,
+	IMX_SC_R_I2C_3,
+	IMX_SC_R_I2C_4,
+	IMX_SC_R_ADC_0,
+	IMX_SC_R_ADC_1,
+	IMX_SC_R_FTM_0,
+	IMX_SC_R_FTM_1,
+	IMX_SC_R_CAN_0,
+	IMX_SC_R_GPU_0_PID0,
+	IMX_SC_R_GPU_1_PID0,
+	IMX_SC_R_PWM_0,
+	IMX_SC_R_PWM_1,
+	IMX_SC_R_PWM_2,
+	IMX_SC_R_PWM_3,
+	IMX_SC_R_PWM_4,
+	IMX_SC_R_PWM_5,
+	IMX_SC_R_PWM_6,
+	IMX_SC_R_PWM_7,
+	IMX_SC_R_GPT_0,
+	IMX_SC_R_GPT_1,
+	IMX_SC_R_GPT_2,
+	IMX_SC_R_GPT_3,
+	IMX_SC_R_GPT_4,
+	IMX_SC_R_FSPI_0,
+	IMX_SC_R_FSPI_1,
+	IMX_SC_R_SDHC_0,
+	IMX_SC_R_SDHC_1,
+	IMX_SC_R_SDHC_2,
+	IMX_SC_R_ENET_0,
+	IMX_SC_R_ENET_1,
+	IMX_SC_R_MLB_0,
+	IMX_SC_R_USB_2,
+	IMX_SC_R_NAND,
+	IMX_SC_R_LVDS_0,
+	IMX_SC_R_LVDS_0_PWM_0,
+	IMX_SC_R_LVDS_0_I2C_0,
+	IMX_SC_R_LVDS_0_I2C_1,
+	IMX_SC_R_LVDS_1,
+	IMX_SC_R_LVDS_1_PWM_0,
+	IMX_SC_R_LVDS_1_I2C_0,
+	IMX_SC_R_LVDS_1_I2C_1,
+	IMX_SC_R_M4_0_I2C,
+	IMX_SC_R_M4_1_I2C,
+	IMX_SC_R_AUDIO_PLL_0,
+	IMX_SC_R_VPU_UART,
+	IMX_SC_R_VPUCORE,
+	IMX_SC_R_MIPI_0,
+	IMX_SC_R_MIPI_0_PWM_0,
+	IMX_SC_R_MIPI_0_I2C_0,
+	IMX_SC_R_MIPI_0_I2C_1,
+	IMX_SC_R_MIPI_1,
+	IMX_SC_R_MIPI_1_PWM_0,
+	IMX_SC_R_MIPI_1_I2C_0,
+	IMX_SC_R_MIPI_1_I2C_1,
+	IMX_SC_R_CSI_0,
+	IMX_SC_R_CSI_0_PWM_0,
+	IMX_SC_R_CSI_0_I2C_0,
+	IMX_SC_R_CSI_1,
+	IMX_SC_R_CSI_1_PWM_0,
+	IMX_SC_R_CSI_1_I2C_0,
+	IMX_SC_R_HDMI,
+	IMX_SC_R_HDMI_I2S,
+	IMX_SC_R_HDMI_I2C_0,
+	IMX_SC_R_HDMI_PLL_0,
+	IMX_SC_R_HDMI_RX,
+	IMX_SC_R_HDMI_RX_BYPASS,
+	IMX_SC_R_HDMI_RX_I2C_0,
+	IMX_SC_R_AUDIO_PLL_1,
+	IMX_SC_R_AUDIO_CLK_0,
+	IMX_SC_R_AUDIO_CLK_1,
+	IMX_SC_R_HDMI_RX_PWM_0,
+	IMX_SC_R_HDMI_PLL_1,
+	IMX_SC_R_VPU,
+};
+
+const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm = {
+	.rsrc = imx8qm_clk_scu_rsrc_table,
+	.num = ARRAY_SIZE(imx8qm_clk_scu_rsrc_table),
+};
diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index 9e35ae45b3a0..88cc737ee125 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -134,6 +134,7 @@  static int imx8qxp_clk_probe(struct platform_device *pdev)
 static const struct of_device_id imx8qxp_match[] = {
 	{ .compatible = "fsl,scu-clk", },
 	{ .compatible = "fsl,imx8qxp-clk", &imx_clk_scu_rsrc_imx8qxp, },
+	{ .compatible = "fsl,imx8qm-clk", &imx_clk_scu_rsrc_imx8qm, },
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/clk/imx/clk-scu.h b/drivers/clk/imx/clk-scu.h
index bcacd8b1d1ab..22156e93b85d 100644
--- a/drivers/clk/imx/clk-scu.h
+++ b/drivers/clk/imx/clk-scu.h
@@ -22,6 +22,7 @@  struct imx_clk_scu_rsrc_table {
 extern struct list_head imx_scu_clks[];
 extern const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops;
 extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp;
+extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm;
 
 int imx_clk_scu_init(struct device_node *np,
 		     const struct imx_clk_scu_rsrc_table *data);