| Message ID | 20210602061739.29134-2-nischal.varide@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enabling dithering after the CC1 | expand |
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Nischal > Varide > Sent: Wednesday, June 2, 2021 11:48 AM > To: intel-gfx@lists.freedesktop.org; Varide, Nischal > <nischal.varide@intel.com>; Shankar, Uma <uma.shankar@intel.com>; Gupta, > Anshuman <anshuman.gupta@intel.com>; Nikula, Jani <jani.nikula@intel.com> > Subject: [Intel-gfx] [PATCH v2 1/1] drm/i915/xelpd: Enabling dithering after > the CC1 > > If the panel is 12bpc then Dithering is not enabled in the Legacy > dithering block , instead its Enabled after the C1 CC1 pipe post > color space conversion.For a 6bpc pannel Dithering is enabled in > Legacy block. > > Signed-off-by: Nischal Varide <nischal.varide@intel.com> > --- > drivers/gpu/drm/i915/display/intel_color.c | 7 +++++++ > drivers/gpu/drm/i915/display/intel_display.c | 7 ++++++- > drivers/gpu/drm/i915/i915_reg.h | 1 + > 3 files changed, 14 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c > b/drivers/gpu/drm/i915/display/intel_color.c > index dab892d2251b..e11b3dbf0b95 100644 > --- a/drivers/gpu/drm/i915/display/intel_color.c > +++ b/drivers/gpu/drm/i915/display/intel_color.c > @@ -1574,6 +1574,7 @@ static int glk_color_check(struct intel_crtc_state > *crtc_state) > static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state) > { > u32 gamma_mode = 0; > + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); > > if (crtc_state->hw.degamma_lut) > gamma_mode |= PRE_CSC_GAMMA_ENABLE; > @@ -1588,6 +1589,12 @@ static u32 icl_gamma_mode(const struct intel_crtc_state > *crtc_state) > else > gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED; > > + if (DISPLAY_VER(i915) >= 13) { > + if (!crtc_state->dither_force_disable && > + (crtc_state->pipe_bpp == 36)) > + gamma_mode |= POST_CC1_GAMMA_ENABLE; > + } > + > return gamma_mode; > } > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index caf0414e0b50..fd3186a5e6ff 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -5762,7 +5762,12 @@ static void bdw_set_pipemisc(const struct > intel_crtc_state *crtc_state) > break; > } > > - if (crtc_state->dither) > + /* > + * If 12bpc panel then, Enables dithering after the CC1 pipe > + * post color space conversion and not here > + */ > + > + if (crtc_state->dither && (crtc_state->pipe_bpp != 36)) Consider we have a config as 12bpc panel + DISPLAY_VER < 13 This check prevents the dither at end of the pipe and apparently icl_gamma_mode() will not enable the dither after CC1. So, we'll end up not enable the Dither at all. > val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; > > if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 24307c49085f..fa800a77ea49 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7743,6 +7743,7 @@ enum { > #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) > #define PRE_CSC_GAMMA_ENABLE (1 << 31) > #define POST_CSC_GAMMA_ENABLE (1 << 30) > +#define POST_CC1_GAMMA_ENABLE (1 << 26) > #define GAMMA_MODE_MODE_MASK (3 << 0) > #define GAMMA_MODE_MODE_8BIT (0 << 0) > #define GAMMA_MODE_MODE_10BIT (1 << 0) > -- > 2.29.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
v3 : Addressed Review Comments by (Bhanu) If the panel is 12bpc then Dithering is not enabled in the Legacy dithering block , instead its Enabled after the C1 CC1 pipe post color space conversion.For a 6bpc pannel Dithering is enabled in Legacy block. If the panel is 12bpc and display_ver < 13 then we can not enable dithering at all.So this v3 version of the patch has added an extra check to fix it. Nischal Varide (1): drm/i915/xelpd: Enabling dithering after the CC1 drivers/gpu/drm/i915/display/intel_color.c | 7 +++++++ drivers/gpu/drm/i915/display/intel_display.c | 11 ++++++++++- drivers/gpu/drm/i915/i915_reg.h | 1 + 3 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index dab892d2251b..e11b3dbf0b95 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1574,6 +1574,7 @@ static int glk_color_check(struct intel_crtc_state *crtc_state) static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state) { u32 gamma_mode = 0; + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); if (crtc_state->hw.degamma_lut) gamma_mode |= PRE_CSC_GAMMA_ENABLE; @@ -1588,6 +1589,12 @@ static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state) else gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED; + if (DISPLAY_VER(i915) >= 13) { + if (!crtc_state->dither_force_disable && + (crtc_state->pipe_bpp == 36)) + gamma_mode |= POST_CC1_GAMMA_ENABLE; + } + return gamma_mode; } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index caf0414e0b50..fd3186a5e6ff 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5762,7 +5762,12 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) break; } - if (crtc_state->dither) + /* + * If 12bpc panel then, Enables dithering after the CC1 pipe + * post color space conversion and not here + */ + + if (crtc_state->dither && (crtc_state->pipe_bpp != 36)) val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 24307c49085f..fa800a77ea49 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7743,6 +7743,7 @@ enum { #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) #define PRE_CSC_GAMMA_ENABLE (1 << 31) #define POST_CSC_GAMMA_ENABLE (1 << 30) +#define POST_CC1_GAMMA_ENABLE (1 << 26) #define GAMMA_MODE_MODE_MASK (3 << 0) #define GAMMA_MODE_MODE_8BIT (0 << 0) #define GAMMA_MODE_MODE_10BIT (1 << 0)
If the panel is 12bpc then Dithering is not enabled in the Legacy dithering block , instead its Enabled after the C1 CC1 pipe post color space conversion.For a 6bpc pannel Dithering is enabled in Legacy block. Signed-off-by: Nischal Varide <nischal.varide@intel.com> --- drivers/gpu/drm/i915/display/intel_color.c | 7 +++++++ drivers/gpu/drm/i915/display/intel_display.c | 7 ++++++- drivers/gpu/drm/i915/i915_reg.h | 1 + 3 files changed, 14 insertions(+), 1 deletion(-)