Message ID | 20210611190111.121295-1-ben.widawsky@intel.com |
---|---|
State | Accepted |
Commit | 6423035fd26c1ecb72f90ecab909e9afa36942b8 |
Headers | show |
Series | [v2] cxl/hdm: Fix decoder count calculation | expand |
On Fri, Jun 11, 2021 at 12:01 PM Ben Widawsky <ben.widawsky@intel.com> wrote: > > The decoder count in the HDM decoder capability structure is an encoded > field. As defined in the spec: > > Decoder Count: Reports the number of memory address decoders implemented > by the component. > 0 – 1 Decoder > 1 – 2 Decoders > 2 – 4 Decoders > 3 – 6 Decoders > 4 – 8 Decoders > 5 – 10 Decoders > All other values are reserved > > Nothing is actually fixed by this as nothing actually used this mapping > yet. I'll still add the Fixes tag because the original commit is broken even if the impact of fixing this bug is moot in the near term.
diff --git a/drivers/cxl/core.c b/drivers/cxl/core.c index 6db660249cea..49744ad885de 100644 --- a/drivers/cxl/core.c +++ b/drivers/cxl/core.c @@ -603,7 +603,7 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base, hdr = readl(register_block); - decoder_cnt = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, hdr); + decoder_cnt = cxl_hdm_decoder_count(hdr); length = 0x20 * decoder_cnt + 0x10; map->hdm_decoder.valid = true; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 3f9a6f7b05db..f1e52487c644 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -42,6 +42,13 @@ #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET 0x1c #define CXL_HDM_DECODER0_CTRL_OFFSET 0x20 +static inline int cxl_hdm_decoder_count(u32 cap_hdr) +{ + int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr); + + return val ? val * 2 : 1; +} + /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ #define CXLDEV_CAP_ARRAY_OFFSET 0x0 #define CXLDEV_CAP_ARRAY_CAP_ID 0