Message ID | 20210611113642.18457-3-biju.das.jz@bp.renesas.com (mailing list archive) |
---|---|
State | Awaiting Upstream, archived |
Headers | show |
Series | None | expand |
On Fri, Jun 11, 2021 at 1:36 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > Add DMAC clock entry in CPG driver. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk-for-v5.15. Gr{oetje,eeting}s, Geert
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 50b5269586a4..04123908511c 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -85,6 +85,9 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { DEF_MOD("ia55", R9A07G044_CLK_IA55, R9A07G044_CLK_P1, 0x518, (BIT(0) | BIT(1)), BIT(0)), + DEF_MOD("dmac", R9A07G044_CLK_DMAC, + R9A07G044_CLK_P1, + 0x52c, (BIT(0) | BIT(1)), (BIT(0) | BIT(1))), DEF_MOD("scif0", R9A07G044_CLK_SCIF0, R9A07G044_CLK_P0, 0x584, BIT(0), BIT(0)),