| Message ID | 20210611165624.30749-3-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add RZ/G2L I2C support | expand |
On Fri, Jun 11, 2021 at 6:56 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > Add I2C{0,1,2.3} clock entries. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk-for-v5.15. Gr{oetje,eeting}s, Geert
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 2d2bc78b84a2..c3136da53614 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -94,6 +94,18 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { DEF_MOD("usb1", R9A07G044_CLK_USB1, R9A07G044_CLK_P1, 0x578, (BIT(1) | BIT(3)), (BIT(1) | BIT(3))), + DEF_MOD("i2c0", R9A07G044_CLK_I2C0, + R9A07G044_CLK_P0, + 0x580, BIT(0), BIT(0)), + DEF_MOD("i2c1", R9A07G044_CLK_I2C1, + R9A07G044_CLK_P0, + 0x580, BIT(1), BIT(1)), + DEF_MOD("i2c2", R9A07G044_CLK_I2C2, + R9A07G044_CLK_P0, + 0x580, BIT(2), BIT(2)), + DEF_MOD("i2c3", R9A07G044_CLK_I2C3, + R9A07G044_CLK_P0, + 0x580, BIT(3), BIT(3)), DEF_MOD("scif0", R9A07G044_CLK_SCIF0, R9A07G044_CLK_P0, 0x584, BIT(0), BIT(0)),
Add I2C{0,1,2.3} clock entries. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/clk/renesas/r9a07g044-cpg.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)