| Message ID | 48f1b59105e46f04b38347fc1555bb5c8d654cff.1623800340.git.alison.schofield@intel.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | CXL ACPI tables for object creation | expand |
On 21-06-15 17:20:39, Alison Schofield wrote: > The ACPI CXL Early Discovery Table (CEDT) includes a list of CXL memory > resources in CXL Fixed Memory Window Structures (CFMWS). Retrieve each > CFMWS in the CEDT and add a cxl_decoder object to the root port (root0) > for each memory resource. > > Signed-off-by: Alison Schofield <alison.schofield@intel.com> > --- > drivers/cxl/acpi.c | 114 +++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 114 insertions(+) > > diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c > index b6d9cd45428c..e3aa356d4dcd 100644 > --- a/drivers/cxl/acpi.c > +++ b/drivers/cxl/acpi.c > @@ -8,8 +8,120 @@ > #include <linux/pci.h> > #include "cxl.h" > > +/* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ > +#define CFMWS_INTERLEAVE_WAYS(x) (1 << (x)->interleave_ways) > +#define CFMWS_INTERLEAVE_GRANULARITY(x) ((x)->granularity + 8) > + > static struct acpi_table_header *cedt_table; > > +static unsigned long cfmws_to_decoder_flags(int restrictions) > +{ > + unsigned long flags = 0; > + > + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE2) > + flags |= CXL_DECODER_F_TYPE2; > + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE3) > + flags |= CXL_DECODER_F_TYPE3; > + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE) > + flags |= CXL_DECODER_F_RAM; > + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_PMEM) > + flags |= CXL_DECODER_F_PMEM; > + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_FIXED) > + flags |= CXL_DECODER_F_LOCK; > + > + return flags; > +} I know these flags aren't introduced by this patch, but I'm wondering if it makes sense to not just use the spec definitions rather than defining our own. It doesn't do much harm, but it's extra typing everytime the spec adds new flags and I don't really see the upside. > + > +static int cxl_acpi_cfmws_verify(struct device *dev, > + struct acpi_cedt_cfmws *cfmws) > +{ > + int expected_len; > + > + if (cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_MODULO) { > + dev_err(dev, "CFMWS Unsupported Interleave Arithmetic\n"); > + return -EINVAL; > + } > + > + if (!IS_ALIGNED(cfmws->base_hpa, SZ_256M)) { > + dev_err(dev, "CFMWS Base HPA not 256MB aligned\n"); > + return -EINVAL; > + } > + > + if (!IS_ALIGNED(cfmws->window_size, SZ_256M)) { > + dev_err(dev, "CFMWS Window Size not 256MB aligned\n"); > + return -EINVAL; > + } > + > + expected_len = struct_size((cfmws), interleave_targets, > + CFMWS_INTERLEAVE_WAYS(cfmws)); > + > + if (expected_len != cfmws->header.length) { I'd switch this to: if (expected_len < cfmws->header.length) If it's too big, just print a dev_dbg. > + dev_err(dev, "CFMWS interleave ways and targets mismatch\n"); > + return -EINVAL; > + } > + > + return 0; > +} > + > +static void cxl_add_cfmws_decoders(struct device *dev, > + struct cxl_port *root_port) > +{ > + struct acpi_cedt_cfmws *cfmws; > + struct cxl_decoder *cxld; > + acpi_size len, cur = 0; > + void *cedt_base; > + int rc; > + > + len = cedt_table->length - sizeof(*cedt_table); > + cedt_base = cedt_table + 1; naming suggestions per previous patch... up to you though. > + > + while (cur < len) { > + struct acpi_cedt_header *c = cedt_base + cur; > + > + if (c->type != ACPI_CEDT_TYPE_CFMWS) { > + cur += c->length; > + continue; > + } > + > + cfmws = cedt_base + cur; > + > + if (cfmws->header.length < sizeof(*cfmws)) { > + dev_err(dev, "Invalid CFMWS header length %u\n", > + cfmws->header.length); > + dev_err(dev, "Failed to add decoders\n"); > + return; > + } > + > + rc = cxl_acpi_cfmws_verify(dev, cfmws); > + if (rc) { > + dev_err(dev, "CFMWS range %#llx-%#llx not registered\n", > + cfmws->base_hpa, cfmws->base_hpa + > + cfmws->window_size - 1); > + cur += c->length; > + continue; > + } > + > + cxld = devm_cxl_add_decoder(dev, root_port, > + CFMWS_INTERLEAVE_WAYS(cfmws), > + cfmws->base_hpa, cfmws->window_size, > + CFMWS_INTERLEAVE_WAYS(cfmws), Interesting... this made me question, how can we have a different number of targets and ways? > + CFMWS_INTERLEAVE_GRANULARITY(cfmws), > + CXL_DECODER_EXPANDER, > + cfmws_to_decoder_flags(cfmws->restrictions)); > + > + if (IS_ERR(cxld)) { > + dev_err(dev, "Failed to add decoder for %#llx-%#llx\n", > + cfmws->base_hpa, cfmws->base_hpa + > + cfmws->window_size - 1); > + } else { > + dev_dbg(dev, "add: %s range %#llx-%#llx\n", > + dev_name(&cxld->dev), cfmws->base_hpa, > + cfmws->base_hpa + cfmws->window_size - 1); > + } > + cur += c->length; > + } > +} > + > static struct acpi_cedt_chbs *cxl_acpi_match_chbs(struct device *dev, u32 uid) > { > struct acpi_cedt_chbs *chbs, *chbs_match = NULL; > @@ -251,6 +363,8 @@ static int cxl_acpi_probe(struct platform_device *pdev) > if (rc) > goto out; > > + cxl_add_cfmws_decoders(host, root_port); > + > /* > * Root level scanned with host-bridge as dports, now scan host-bridges > * for their role as CXL uports to their CXL-capable PCIe Root Ports. > -- > 2.26.2 >
On Wed, Jun 16, 2021 at 9:17 AM Ben Widawsky <ben.widawsky@intel.com> wrote: > > On 21-06-15 17:20:39, Alison Schofield wrote: > > The ACPI CXL Early Discovery Table (CEDT) includes a list of CXL memory > > resources in CXL Fixed Memory Window Structures (CFMWS). Retrieve each > > CFMWS in the CEDT and add a cxl_decoder object to the root port (root0) > > for each memory resource. > > > > Signed-off-by: Alison Schofield <alison.schofield@intel.com> > > --- > > drivers/cxl/acpi.c | 114 +++++++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 114 insertions(+) > > > > diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c > > index b6d9cd45428c..e3aa356d4dcd 100644 > > --- a/drivers/cxl/acpi.c > > +++ b/drivers/cxl/acpi.c > > @@ -8,8 +8,120 @@ > > #include <linux/pci.h> > > #include "cxl.h" > > > > +/* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ > > +#define CFMWS_INTERLEAVE_WAYS(x) (1 << (x)->interleave_ways) > > +#define CFMWS_INTERLEAVE_GRANULARITY(x) ((x)->granularity + 8) > > + > > static struct acpi_table_header *cedt_table; > > > > +static unsigned long cfmws_to_decoder_flags(int restrictions) > > +{ > > + unsigned long flags = 0; > > + > > + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE2) > > + flags |= CXL_DECODER_F_TYPE2; > > + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE3) > > + flags |= CXL_DECODER_F_TYPE3; > > + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE) > > + flags |= CXL_DECODER_F_RAM; > > + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_PMEM) > > + flags |= CXL_DECODER_F_PMEM; > > + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_FIXED) > > + flags |= CXL_DECODER_F_LOCK; > > + > > + return flags; > > +} > > I know these flags aren't introduced by this patch, but I'm wondering if it > makes sense to not just use the spec definitions rather than defining our own. > It doesn't do much harm, but it's extra typing everytime the spec adds new flags > and I don't really see the upside. The flags are bounded by what's in HDM decoders, I don't see them moving so fast that the kernel can not keep up. The rationale for the split is the same as the split between ACPI NFIT and the LIBNVDIMM core. The ACPI specifics are just one way to convey a common platform attribute to the core. In fact this was one of the main feedbacks of the initial "ND" subsystem which eventually became LIBNVDIMM [1]. ND stood for "NFIT Defined" and the arch split between ACPI specific and Linux translation has paid off over the years. [1]: https://lore.kernel.org/lkml/20150420070624.GB13876@gmail.com/ > > > + > > +static int cxl_acpi_cfmws_verify(struct device *dev, > > + struct acpi_cedt_cfmws *cfmws) > > +{ > > + int expected_len; > > + > > + if (cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_MODULO) { > > + dev_err(dev, "CFMWS Unsupported Interleave Arithmetic\n"); > > + return -EINVAL; > > + } > > + > > + if (!IS_ALIGNED(cfmws->base_hpa, SZ_256M)) { > > + dev_err(dev, "CFMWS Base HPA not 256MB aligned\n"); > > + return -EINVAL; > > + } > > + > > + if (!IS_ALIGNED(cfmws->window_size, SZ_256M)) { > > + dev_err(dev, "CFMWS Window Size not 256MB aligned\n"); > > + return -EINVAL; > > + } > > + > > + expected_len = struct_size((cfmws), interleave_targets, > > + CFMWS_INTERLEAVE_WAYS(cfmws)); > > + > > + if (expected_len != cfmws->header.length) { > > I'd switch this to: > if (expected_len < cfmws->header.length) > > If it's too big, just print a dev_dbg. Maybe call it min_len then? [..] > > + > > + cxld = devm_cxl_add_decoder(dev, root_port, > > + CFMWS_INTERLEAVE_WAYS(cfmws), > > + cfmws->base_hpa, cfmws->window_size, > > + CFMWS_INTERLEAVE_WAYS(cfmws), > > Interesting... this made me question, how can we have a different number of > targets and ways? These settings can be changed later on a switch-level decoder, for a root-level decoder these initial values are fixed.
On Tue, 15 Jun 2021 17:20:39 -0700 Alison Schofield <alison.schofield@intel.com> wrote: > The ACPI CXL Early Discovery Table (CEDT) includes a list of CXL memory > resources in CXL Fixed Memory Window Structures (CFMWS). Retrieve each > CFMWS in the CEDT and add a cxl_decoder object to the root port (root0) > for each memory resource. > > Signed-off-by: Alison Schofield <alison.schofield@intel.com> LGTM Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > drivers/cxl/acpi.c | 114 +++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 114 insertions(+) > > diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c > index b6d9cd45428c..e3aa356d4dcd 100644 > --- a/drivers/cxl/acpi.c > +++ b/drivers/cxl/acpi.c > @@ -8,8 +8,120 @@ > #include <linux/pci.h> > #include "cxl.h" > > +/* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ > +#define CFMWS_INTERLEAVE_WAYS(x) (1 << (x)->interleave_ways) > +#define CFMWS_INTERLEAVE_GRANULARITY(x) ((x)->granularity + 8) > + > static struct acpi_table_header *cedt_table; > > +static unsigned long cfmws_to_decoder_flags(int restrictions) > +{ > + unsigned long flags = 0; > + > + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE2) > + flags |= CXL_DECODER_F_TYPE2; > + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE3) > + flags |= CXL_DECODER_F_TYPE3; > + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE) > + flags |= CXL_DECODER_F_RAM; > + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_PMEM) > + flags |= CXL_DECODER_F_PMEM; > + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_FIXED) > + flags |= CXL_DECODER_F_LOCK; > + > + return flags; > +} > + > +static int cxl_acpi_cfmws_verify(struct device *dev, > + struct acpi_cedt_cfmws *cfmws) > +{ > + int expected_len; > + > + if (cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_MODULO) { > + dev_err(dev, "CFMWS Unsupported Interleave Arithmetic\n"); > + return -EINVAL; > + } > + > + if (!IS_ALIGNED(cfmws->base_hpa, SZ_256M)) { > + dev_err(dev, "CFMWS Base HPA not 256MB aligned\n"); > + return -EINVAL; > + } > + > + if (!IS_ALIGNED(cfmws->window_size, SZ_256M)) { > + dev_err(dev, "CFMWS Window Size not 256MB aligned\n"); > + return -EINVAL; > + } > + > + expected_len = struct_size((cfmws), interleave_targets, > + CFMWS_INTERLEAVE_WAYS(cfmws)); > + > + if (expected_len != cfmws->header.length) { > + dev_err(dev, "CFMWS interleave ways and targets mismatch\n"); > + return -EINVAL; > + } > + > + return 0; > +} > + > +static void cxl_add_cfmws_decoders(struct device *dev, > + struct cxl_port *root_port) > +{ > + struct acpi_cedt_cfmws *cfmws; > + struct cxl_decoder *cxld; > + acpi_size len, cur = 0; > + void *cedt_base; > + int rc; > + > + len = cedt_table->length - sizeof(*cedt_table); > + cedt_base = cedt_table + 1; > + > + while (cur < len) { > + struct acpi_cedt_header *c = cedt_base + cur; > + > + if (c->type != ACPI_CEDT_TYPE_CFMWS) { > + cur += c->length; > + continue; > + } > + > + cfmws = cedt_base + cur; > + > + if (cfmws->header.length < sizeof(*cfmws)) { > + dev_err(dev, "Invalid CFMWS header length %u\n", > + cfmws->header.length); > + dev_err(dev, "Failed to add decoders\n"); > + return; > + } > + > + rc = cxl_acpi_cfmws_verify(dev, cfmws); > + if (rc) { > + dev_err(dev, "CFMWS range %#llx-%#llx not registered\n", > + cfmws->base_hpa, cfmws->base_hpa + > + cfmws->window_size - 1); > + cur += c->length; > + continue; > + } > + > + cxld = devm_cxl_add_decoder(dev, root_port, > + CFMWS_INTERLEAVE_WAYS(cfmws), > + cfmws->base_hpa, cfmws->window_size, > + CFMWS_INTERLEAVE_WAYS(cfmws), > + CFMWS_INTERLEAVE_GRANULARITY(cfmws), > + CXL_DECODER_EXPANDER, > + cfmws_to_decoder_flags(cfmws->restrictions)); > + > + if (IS_ERR(cxld)) { > + dev_err(dev, "Failed to add decoder for %#llx-%#llx\n", > + cfmws->base_hpa, cfmws->base_hpa + > + cfmws->window_size - 1); > + } else { > + dev_dbg(dev, "add: %s range %#llx-%#llx\n", > + dev_name(&cxld->dev), cfmws->base_hpa, > + cfmws->base_hpa + cfmws->window_size - 1); > + } > + cur += c->length; > + } > +} > + > static struct acpi_cedt_chbs *cxl_acpi_match_chbs(struct device *dev, u32 uid) > { > struct acpi_cedt_chbs *chbs, *chbs_match = NULL; > @@ -251,6 +363,8 @@ static int cxl_acpi_probe(struct platform_device *pdev) > if (rc) > goto out; > > + cxl_add_cfmws_decoders(host, root_port); > + > /* > * Root level scanned with host-bridge as dports, now scan host-bridges > * for their role as CXL uports to their CXL-capable PCIe Root Ports.
Thanks for the review Ben - On Wed, Jun 16, 2021 at 09:17:40AM -0700, Ben Widawsky wrote: > On 21-06-15 17:20:39, Alison Schofield wrote: snip > > +static unsigned long cfmws_to_decoder_flags(int restrictions) > > +{ > > + unsigned long flags = 0; > > + > > + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE2) > > + flags |= CXL_DECODER_F_TYPE2; > > + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE3) > > + flags |= CXL_DECODER_F_TYPE3; > > + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE) > > + flags |= CXL_DECODER_F_RAM; > > + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_PMEM) > > + flags |= CXL_DECODER_F_PMEM; > > + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_FIXED) > > + flags |= CXL_DECODER_F_LOCK; > > + > > + return flags; > > +} > > I know these flags aren't introduced by this patch, but I'm wondering if it > makes sense to not just use the spec definitions rather than defining our own. > It doesn't do much harm, but it's extra typing everytime the spec adds new flags > and I don't really see the upside. > I think Dan's email in this thread covered this. snip > > + > > +static int cxl_acpi_cfmws_verify(struct device *dev, > > + struct acpi_cedt_cfmws *cfmws) > > +{ snip > > + > > + > > + expected_len = struct_size((cfmws), interleave_targets, > > + CFMWS_INTERLEAVE_WAYS(cfmws)); > > + > > + if (expected_len != cfmws->header.length) { > > I'd switch this to: > if (expected_len < cfmws->header.length) > > If it's too big, just print a dev_dbg. > Got it. snip > > + void *cedt_base; > > + int rc; > > + > > + len = cedt_table->length - sizeof(*cedt_table); > > + cedt_base = cedt_table + 1; > > naming suggestions per previous patch... up to you though. > Ditto w previous patch. snip > > + > > + } > > + > > + cxld = devm_cxl_add_decoder(dev, root_port, > > + CFMWS_INTERLEAVE_WAYS(cfmws), > > + cfmws->base_hpa, cfmws->window_size, > > + CFMWS_INTERLEAVE_WAYS(cfmws), > > Interesting... this made me question, how can we have a different number of > targets and ways? > Dan explained this previously: "nr_targets is the number of possible targets that this decoder can target. For CFMWS it just equals interleave_ways because the target list can't be changed. A switch on the other hand could support up to 16 possible targets, but be dynamically configured to only do a 1-way interleave. So this is an artifact of 'struct cxl_decoder' representing both fixed CFMWS entries and dynamically programmable switch entries. nr_targets tells devm_cxl_add_decoder() how much memory to allocate for its target list, interleave_ways tells devm_cxl_add_decoder() what the decoder is currently programmed to decode." > snip >
diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index b6d9cd45428c..e3aa356d4dcd 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -8,8 +8,120 @@ #include <linux/pci.h> #include "cxl.h" +/* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ +#define CFMWS_INTERLEAVE_WAYS(x) (1 << (x)->interleave_ways) +#define CFMWS_INTERLEAVE_GRANULARITY(x) ((x)->granularity + 8) + static struct acpi_table_header *cedt_table; +static unsigned long cfmws_to_decoder_flags(int restrictions) +{ + unsigned long flags = 0; + + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE2) + flags |= CXL_DECODER_F_TYPE2; + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE3) + flags |= CXL_DECODER_F_TYPE3; + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE) + flags |= CXL_DECODER_F_RAM; + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_PMEM) + flags |= CXL_DECODER_F_PMEM; + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_FIXED) + flags |= CXL_DECODER_F_LOCK; + + return flags; +} + +static int cxl_acpi_cfmws_verify(struct device *dev, + struct acpi_cedt_cfmws *cfmws) +{ + int expected_len; + + if (cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_MODULO) { + dev_err(dev, "CFMWS Unsupported Interleave Arithmetic\n"); + return -EINVAL; + } + + if (!IS_ALIGNED(cfmws->base_hpa, SZ_256M)) { + dev_err(dev, "CFMWS Base HPA not 256MB aligned\n"); + return -EINVAL; + } + + if (!IS_ALIGNED(cfmws->window_size, SZ_256M)) { + dev_err(dev, "CFMWS Window Size not 256MB aligned\n"); + return -EINVAL; + } + + expected_len = struct_size((cfmws), interleave_targets, + CFMWS_INTERLEAVE_WAYS(cfmws)); + + if (expected_len != cfmws->header.length) { + dev_err(dev, "CFMWS interleave ways and targets mismatch\n"); + return -EINVAL; + } + + return 0; +} + +static void cxl_add_cfmws_decoders(struct device *dev, + struct cxl_port *root_port) +{ + struct acpi_cedt_cfmws *cfmws; + struct cxl_decoder *cxld; + acpi_size len, cur = 0; + void *cedt_base; + int rc; + + len = cedt_table->length - sizeof(*cedt_table); + cedt_base = cedt_table + 1; + + while (cur < len) { + struct acpi_cedt_header *c = cedt_base + cur; + + if (c->type != ACPI_CEDT_TYPE_CFMWS) { + cur += c->length; + continue; + } + + cfmws = cedt_base + cur; + + if (cfmws->header.length < sizeof(*cfmws)) { + dev_err(dev, "Invalid CFMWS header length %u\n", + cfmws->header.length); + dev_err(dev, "Failed to add decoders\n"); + return; + } + + rc = cxl_acpi_cfmws_verify(dev, cfmws); + if (rc) { + dev_err(dev, "CFMWS range %#llx-%#llx not registered\n", + cfmws->base_hpa, cfmws->base_hpa + + cfmws->window_size - 1); + cur += c->length; + continue; + } + + cxld = devm_cxl_add_decoder(dev, root_port, + CFMWS_INTERLEAVE_WAYS(cfmws), + cfmws->base_hpa, cfmws->window_size, + CFMWS_INTERLEAVE_WAYS(cfmws), + CFMWS_INTERLEAVE_GRANULARITY(cfmws), + CXL_DECODER_EXPANDER, + cfmws_to_decoder_flags(cfmws->restrictions)); + + if (IS_ERR(cxld)) { + dev_err(dev, "Failed to add decoder for %#llx-%#llx\n", + cfmws->base_hpa, cfmws->base_hpa + + cfmws->window_size - 1); + } else { + dev_dbg(dev, "add: %s range %#llx-%#llx\n", + dev_name(&cxld->dev), cfmws->base_hpa, + cfmws->base_hpa + cfmws->window_size - 1); + } + cur += c->length; + } +} + static struct acpi_cedt_chbs *cxl_acpi_match_chbs(struct device *dev, u32 uid) { struct acpi_cedt_chbs *chbs, *chbs_match = NULL; @@ -251,6 +363,8 @@ static int cxl_acpi_probe(struct platform_device *pdev) if (rc) goto out; + cxl_add_cfmws_decoders(host, root_port); + /* * Root level scanned with host-bridge as dports, now scan host-bridges * for their role as CXL uports to their CXL-capable PCIe Root Ports.
The ACPI CXL Early Discovery Table (CEDT) includes a list of CXL memory resources in CXL Fixed Memory Window Structures (CFMWS). Retrieve each CFMWS in the CEDT and add a cxl_decoder object to the root port (root0) for each memory resource. Signed-off-by: Alison Schofield <alison.schofield@intel.com> --- drivers/cxl/acpi.c | 114 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 114 insertions(+)